文件名称:i2c
介绍说明－－下载内容均来自于网络，请自行研究使用
代码中是用于实现基于FPGA的I2C的通信实验，可移植性强-Code is used to implement the FPGA based I2C communication experiment, portability strong
(系统自动生成,下载前可以参看下载内容)
下载文件列表
i2c\bench\CVS\Entries
...\.....\...\Repository
...\.....\...\Root
...\.....\verilog\CVS\Entries
...\.....\.......\...\Repository
...\.....\.......\...\Root
...\.....\.......\i2c_slave_model.v
...\.....\.......\i2c_slave_model.v.bak
...\.....\.......\spi_slave_model.v
...\.....\.......\spi_slave_model.v.bak
...\.....\.......\tst_bench_top.v
...\.....\.......\tst_bench_top.v.bak
...\.....\.......\wb_master_model.v
...\.....\.......\wb_master_model.v.bak
...\CVS\Entries
...\...\Repository
...\...\Root
...\doc\CVS\Entries
...\...\...\Repository
...\...\...\Root
...\...\i2c_specs.pdf
...\...\src\CVS\Entries
...\...\...\...\Repository
...\...\...\...\Root
...\...\...\I2C_specs.doc
...\rtl\CVS\Entries
...\...\...\Repository
...\...\...\Root
...\...\verilog\CVS\Entries
...\...\.......\...\Repository
...\...\.......\...\Root
...\...\.......\i2c_master_bit_ctrl.v
...\...\.......\i2c_master_bit_ctrl.v.bak
...\...\.......\i2c_master_byte_ctrl.v
...\...\.......\i2c_master_byte_ctrl.v.bak
...\...\.......\i2c_master_defines.v
...\...\.......\i2c_master_top.v
...\...\.......\i2c_master_top.v.bak
...\...\.......\timescale.v
...\...\.hdl\CVS\Entries
...\...\....\...\Repository
...\...\....\...\Root
...\...\....\I2C.VHD
...\...\....\i2c_master_bit_ctrl.vhd
...\...\....\i2c_master_byte_ctrl.vhd
...\...\....\i2c_master_top.vhd
...\...\....\readme
...\...\....\tst_ds1621.vhd
...\sim\CVS\Entries
...\...\...\Repository
...\...\...\Root
...\...\i2c.cr.mti
...\...\i2c.mpf
...\...\..._verilog\CVS\Entries
...\...\...........\...\Repository
...\...\...........\...\Root
...\...\...........\run\bench.vcd
...\...\...........\...\CVS\Entries
...\...\...........\...\...\Repository
...\...\...........\...\...\Root
...\...\...........\...\INCA_libs\CVS\Entries
...\...\...........\...\.........\...\Repository
...\...\...........\...\.........\...\Root
...\...\...........\...\ncverilog.key
...\...\...........\...\ncverilog.log
...\...\...........\...\run
...\...\...........\...\waves\CVS\Entries
...\...\...........\...\.....\...\Repository
...\...\...........\...\.....\...\Root
...\...\vsim.wlf
...\...\work\@m@a@x@i@i_@p@r@i@m_@d@f@f@e\verilog.asm
...\...\....\............................\_primary.dat
...\...\....\............................\_primary.vhd
...\...\....\delay\verilog.asm
...\...\....\.....\_primary.dat
...\...\....\.....\_primary.vhd
...\...\....\i2c_master_bit_ctrl\verilog.asm
...\...\....\...................\_primary.dat
...\...\....\...................\_primary.vhd
...\...\....\............yte_ctrl\verilog.asm
...\...\....\....................\_primary.dat
...\...\....\....................\_primary.vhd
...\...\....\...........top\verilog.asm
...\...\....\..............\_primary.dat
...\...\....\..............\_primary.vhd
...\...\....\....slave_model\verilog.asm
...\...\....\...............\_primary.dat
...\...\....\...............\_primary.vhd
...\...\....\maxii_and1\verilog.asm
...\...\....\..........\_primary.dat
...\...\....\..........\_primary.vhd
...\...\....\..........6\verilog.asm
...\...\....\...........\_primary.dat
...\...\....\...........\_primary.vhd
...\...\....\.......synch_lcell\verilog.asm
...\...\....\..................\_primary.dat
...\...\....\..................\_primary.vhd
...\...\....\......b17mux21\verilog.asm
...\...\....\..............\_primary.dat
...\...\....\..............\_primary.vhd