文件名称:verilog9999
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Verilog 实现9999计数，内有分频模块，计数模块，译码，动态显示扫描等，用数码显示，
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压缩包 : 59564351verilog9999.rar 列表 verilog9999\jishu0.qpf verilog9999\jishu0.qsf verilog9999\jishu0.map.rpt verilog9999\jishu0.flow.rpt verilog9999\jishu0.map.summary verilog9999\jishu0.pin verilog9999\jishu0.fit.rpt verilog9999\jishu0.fit.smsg verilog9999\jishu0.fit.summary verilog9999\jishu0.pof verilog9999\jishu0.asm.rpt verilog9999\jishu0.tan.summary verilog9999\jishu0.tan.rpt verilog9999\jishu0.done verilog9999\jishu0.vwf verilog9999\jishu0.sim.rpt verilog9999\yima.v verilog9999\yima.bsf verilog9999\jishu0.bsf verilog9999\dis.v verilog9999\jishu0.qws verilog9999\dis.bsf verilog9999\fegpin.v verilog9999\jishu0.map.smsg verilog9999\fengpin1.bsf verilog9999\fengpin.bsf verilog9999\jishu0.dpf verilog9999\jishu0.cdf verilog9999\fen.bsf verilog9999\mux.v verilog9999\mux.bsf verilog9999\dispselect.v verilog9999\dispselect.bsf verilog9999\fen1hz.v verilog9999\fen1hz.bsf verilog9999\fen1k.v verilog9999\fen1k.bsf verilog9999\Block1.bdf verilog9999\ji.bsf verilog9999\jishu1.v verilog9999\jishu1.bsf verilog9999\dispselect.inc verilog9999\db\jishu0.db_info verilog9999\db\jishu0.signalprobe.cdb verilog9999\db\jishu0.asm.qmsg verilog9999\db\jishu0.cmp.hdb verilog9999\db\jishu0.(1).cnf.cdb verilog9999\db\jishu0.cbx.xml verilog9999\db\jishu0.hif verilog9999\db\jishu0.sim.qmsg verilog9999\db\jishu0.cmp.tdb verilog9999\db\jishu0.hier_info verilog9999\db\jishu0.(1).cnf.hdb verilog9999\db\jishu0.asm_labs.ddb verilog9999\db\jishu0.tan.qmsg verilog9999\db\jishu0.(0).cnf.cdb verilog9999\db\jishu0.(0).cnf.hdb verilog9999\db\jishu0.(3).cnf.cdb verilog9999\db\jishu0.psp verilog9999\db\jishu0.dbp verilog9999\db\jishu0.(3).cnf.hdb verilog9999\db\jishu0.(2).cnf.cdb verilog9999\db\jishu0.(2).cnf.hdb verilog9999\db\jishu0.syn_hier_info verilog9999\db\jishu0.cmp.rdb verilog9999\db\jishu0.cmp0.ddb verilog9999\db\jishu0.cmp.cdb verilog9999\db\jishu0.(5).cnf.cdb verilog9999\db\jishu0.(6).cnf.cdb verilog9999\db\jishu0.(5).cnf.hdb verilog9999\db\jishu0.cmp.kpt verilog9999\db\jishu0.(6).cnf.hdb verilog9999\db\jishu0.(7).cnf.cdb verilog9999\db\jishu0.(7).cnf.hdb verilog9999\db\jishu0.sim.hdb verilog9999\db\jishu0.sim.vwf verilog9999\db\jishu0.sim.rdb verilog9999\db\jishu0.eds_overflow verilog9999\db\wed.zsf verilog9999\db\jishu0.eco.cdb verilog9999\db\jishu0.map.qmsg verilog9999\db\jishu0.(4).cnf.cdb verilog9999\db\jishu0.(4).cnf.hdb verilog9999\db\jishu0.rtlv_sg.cdb verilog9999\db\jishu0.rtlv.hdb verilog9999\db\jishu0.rtlv_sg_swap.cdb verilog9999\db\jishu0.pre_map.hdb verilog9999\db\jishu0.pre_map.cdb verilog9999\db\jishu0.map.logdb verilog9999\db\jishu0.sgdiff.cdb verilog9999\db\jishu0.sgdiff.hdb verilog9999\db\jishu0.sld_design_entry_dsc.sci verilog9999\db\jishu0.map.cdb verilog9999\db\jishu0.map.hdb verilog9999\db\jishu0.fit.qmsg verilog9999\db\jishu0.cmp.logdb verilog9999\db\jishu0.sld_design_entry.sci verilog9999\db verilog9999