文件名称:20140825
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FPGA设计在设计过程中使用ISE软件自带的IP核时，消耗资源太大的时候，需要自己编写滤波器的源代码，这里给出我们常用的串行FIR核的verilog语言代码设计文件，并通过作者时序仿真验证，并用于实际的项目中。-The FPGA design in the design process of ISE software used to own the IP core, consume resources is too big, need to write your own source code of the filter, presented here we commonly used serial FIR the verilog language code design document, and through the author timing simulation, and used for actual projects
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下载文件列表
20140825\coef.coe
........\data_tb.txt
........\data_tb_sin.m
........\modelsim\d_fir_tb.v
........\........\d_fir_wave.do
........\........\fir_chuan_tb.v
........\........\fir_chuan_wave.do
........\rtl\d_fir_top.v
........\...\fir_chuan.v
........\top\d_fir\coef.coe
........\...\.....\data_tb.txt
........\...\.....\d_fir.gise
........\...\.....\d_fir.xise
........\...\.....\d_fir_tb.fdo
........\...\.....\d_fir_tb.udo
........\...\.....\d_fir_tb_wave.fdo
........\...\.....\d_fir_top.bld
........\...\.....\d_fir_top.cmd_log
........\...\.....\d_fir_top.lso
........\...\.....\d_fir_top.ncd
........\...\.....\d_fir_top.ngc
........\...\.....\d_fir_top.ngd
........\...\.....\d_fir_top.ngr
........\...\.....\d_fir_top.pad
........\...\.....\d_fir_top.par
........\...\.....\d_fir_top.pcf
........\...\.....\d_fir_top.prj
........\...\.....\d_fir_top.ptwx
........\...\.....\d_fir_top.stx
........\...\.....\d_fir_top.syr
........\...\.....\d_fir_top.twr
........\...\.....\d_fir_top.twx
........\...\.....\d_fir_top.unroutes
........\...\.....\d_fir_top.xpi
........\...\.....\d_fir_top.xst
........\...\.....\d_fir_top_envsettings.html
........\...\.....\d_fir_top_guide.ncd
........\...\.....\d_fir_top_map.map
........\...\.....\d_fir_top_map.mrp
........\...\.....\d_fir_top_map.ncd
........\...\.....\d_fir_top_map.ngm
........\...\.....\d_fir_top_map.xrpt
........\...\.....\d_fir_top_ngdbuild.xrpt
........\...\.....\d_fir_top_pad.csv
........\...\.....\d_fir_top_pad.txt
........\...\.....\d_fir_top_par.xrpt
........\...\.....\d_fir_top_summary.html
........\...\.....\d_fir_top_summary.xml
........\...\.....\d_fir_top_usage.xml
........\...\.....\d_fir_top_xst.xrpt
........\...\.....\ipcore_dir\acc\doc\c_accum_v11_0_readme.txt
........\...\.....\..........\...\...\c_accum_v11_0_vinfo.html
........\...\.....\..........\...\...\ds213_accum.pdf
........\...\.....\..........\acc.asy
........\...\.....\..........\acc.gise
........\...\.....\..........\acc.ncf
........\...\.....\..........\acc.ngc
........\...\.....\..........\acc.sym
........\...\.....\..........\acc.v
........\...\.....\..........\acc.veo
........\...\.....\..........\acc.xco
........\...\.....\..........\acc.xise
........\...\.....\..........\acc_flist.txt
........\...\.....\..........\acc_xmdf.tcl
........\...\.....\..........\blk_mem_gen_ds512.pdf
........\...\.....\..........\blk_mem_gen_v6_3_readme.txt
........\...\.....\..........\coef.coe
........\...\.....\..........\coregen.cgp
........\...\.....\..........\coregen.log
........\...\.....\..........\core_resources.txt
........\...\.....\..........\create_acc.tcl
........\...\.....\..........\create_muti.tcl
........\...\.....\..........\create_ram_data_in.tcl
........\...\.....\..........\create_ROM_COEF.tcl
........\...\.....\..........\edit_ram_data_in.tcl
........\...\.....\..........\gui_latency.txt
........\...\.....\..........\muti\doc\mult_gen_ds255.pdf
........\...\.....\..........\....\...\mult_gen_v11_2_readme.txt
........\...\.....\..........\....\...\mult_gen_v11_2_vinfo.html
........\...\.....\..........\muti.asy
........\...\.....\..........\muti.gise
........\...\.....\..........\muti.ncf
........\...\.....\..........\muti.ngc
........\...\.....\..........\muti.sym
........\...\.....\..........\muti.v
........\...\.....\..........\muti.veo
........\...\.....\..........\muti.xco
........\...\.....\..........\muti.xise
........\...\.....\..........\muti_flist.txt
........\...\.....\..........\muti_xmdf.tcl
........\...\.....\..........\ram_data_in\example_design\bmg_wrapper.vhd
........\...\.....\..........\...........\..............\ram_data_in_top.ucf
........\...\.....\..........\...........\..............\ram_data_in_top.vhd
........\...\.....\..........\...........\..............\ram_data_in_top.xdc
........\...\.....\..........\...........\implement\implement.bat
........\...\.....\..........\...........\.........\implement.sh
........\...\.....\..........\...........\.........\planAhead_rdn.bat
........\...\.....\..........\...........\.........\planAhead_rdn.sh
........\...\.....\....