文件名称:fifo_verilog
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16位FIFO的硬件电路，使用verilog实现。文件内含组合逻辑和寄存逻辑两种方法的实现，以及对应的testbench测试代码-16 FIFO hardware circuits using verilog implementation. File contains a combination of logic and storage logic to achieve the two methods, and the corresponding testbench test code
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下载文件列表
vsim.wlf
fifo.v
fifo_withreg.v
tb_fifo.v
tb_fifo_withReg.v
............@reg\verilog.asm
................\_primary.dat
................\_primary.vhd
fifo\verilog.asm
....\_primary.dat
....\_primary.vhd
...._withreg\verilog.asm
............\_primary.dat
............\_primary.vhd
tb_fifo\verilog.asm
.......\_primary.dat
.......\_primary.vhd
tb_fifo_with@reg
fifo
fifo_withreg
tb_fifo