文件名称:1-D-DWT_verilog-code
- 所属分类：
- VHDL编程
- 资源属性：
- [Windows] [Visual C] [源码]
- 上传时间：
- 2014-06-28
- 文件大小：
- 1.41mb
- 下载次数：
- 0次
- 提 供 者：
- jea***
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
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Image compression is one of the prominent topics in image processing that plays a very important role in
reducing image size for real-time transmission and storage. Many of the standards recommend the use of DWT
for image compression. The computational complexity of DWT imposes a major challenge for the real-time use
of DWT-based image compression algorithms. In this paper, we propose a modified lifting scheme for
computing the approximation and detailed coefficients of DWT. The modified equations use, right shift
operators and 6-bit multipliers. The hierarchy levels in computation are reduced to one thereby minimizing the
delay and increasing throughput. The design implemented on Virtex-5 FPGA operates at 180 MHz and
consumes less than 1W of power. The design occupies less than 1 of the LUT resources on FPGA. The
architecture developed is suitable for real-time image processing on FPGA platform.
-Image compression is one of the prominent topics in image processing that plays a very important role in
reducing image size for real-time transmission and storage. Many of the standards recommend the use of DWT
for image compression. The computational complexity of DWT imposes a major challenge for the real-time use
of DWT-based image compression algorithms. In this paper, we propose a modified lifting scheme for
computing the approximation and detailed coefficients of DWT. The modified equations use, right shift
operators and 6-bit multipliers. The hierarchy levels in computation are reduced to one thereby minimizing the
delay and increasing throughput. The design implemented on Virtex-5 FPGA operates at 180 MHz and
consumes less than 1W of power. The design occupies less than 1 of the LUT resources on FPGA. The
architecture developed is suitable for real-time image processing on FPGA platform.
reducing image size for real-time transmission and storage. Many of the standards recommend the use of DWT
for image compression. The computational complexity of DWT imposes a major challenge for the real-time use
of DWT-based image compression algorithms. In this paper, we propose a modified lifting scheme for
computing the approximation and detailed coefficients of DWT. The modified equations use, right shift
operators and 6-bit multipliers. The hierarchy levels in computation are reduced to one thereby minimizing the
delay and increasing throughput. The design implemented on Virtex-5 FPGA operates at 180 MHz and
consumes less than 1W of power. The design occupies less than 1 of the LUT resources on FPGA. The
architecture developed is suitable for real-time image processing on FPGA platform.
-Image compression is one of the prominent topics in image processing that plays a very important role in
reducing image size for real-time transmission and storage. Many of the standards recommend the use of DWT
for image compression. The computational complexity of DWT imposes a major challenge for the real-time use
of DWT-based image compression algorithms. In this paper, we propose a modified lifting scheme for
computing the approximation and detailed coefficients of DWT. The modified equations use, right shift
operators and 6-bit multipliers. The hierarchy levels in computation are reduced to one thereby minimizing the
delay and increasing throughput. The design implemented on Virtex-5 FPGA operates at 180 MHz and
consumes less than 1W of power. The design occupies less than 1 of the LUT resources on FPGA. The
architecture developed is suitable for real-time image processing on FPGA platform.
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下载文件列表
DWT的Verilog code\2Ddwt_ALL\01.raw
.................\.........\02.raw
.................\.........\02.raw.bak
.................\.........\2D_F97_B.raw
.................\.........\BABOO64.raw
.................\.........\Debug\Psnr.exe
.................\.........\.....\Psnr.ilk
.................\.........\.....\Psnr.obj
.................\.........\.....\Psnr.pch
.................\.........\.....\Psnr.pdb
.................\.........\.....\save_FPGAtoPC.exe
.................\.........\.....\save_FPGAtoPC.ilk
.................\.........\.....\save_FPGAtoPC.obj
.................\.........\.....\save_FPGAtoPC.pch
.................\.........\.....\save_FPGAtoPC.pdb
.................\.........\.....\SendPctoFPGA.exe
.................\.........\.....\SendPctoFPGA.ilk
.................\.........\.....\SendPctoFPGA.obj
.................\.........\.....\SendPctoFPGA.pch
.................\.........\.....\SendPctoFPGA.pdb
.................\.........\.....\vc60.idb
.................\.........\.....\vc60.pdb
.................\.........\EARTH128.raw
.................\.........\EARTH128.raw.bak
.................\.........\Kent_End.raw.bak
.................\.........\LENA128.raw
.................\.........\LENA64(no).raw
.................\.........\LENA64(no).raw.bak
.................\.........\LENA64.raw
.................\.........\LENA64.raw.bak
.................\.........\Psnr.cpp
.................\.........\Psnr.dsp
.................\.........\Psnr.dsw
.................\.........\Psnr.ncb
.................\.........\Psnr.opt
.................\.........\Psnr.plg
.................\.........\RAW\2D1L\2D_F1L_Col.raw
.................\.........\...\....\2D_F1L_Row.raw
.................\.........\...\....\2D_I1L_ReSource.raw
.................\.........\...\2D1L_ReSource.raw
.................\.........\...\..2L\2D_F2L_Col.raw
.................\.........\...\....\2D_F2L_Row.raw
.................\.........\...\....\2D_F2L_Row_to_Resource.raw
.................\.........\...\....\2D_FI2L_ReSource.raw
.................\.........\save_FPGAtoPC.cpp
.................\.........\save_FPGAtoPC.dsp
.................\.........\save_FPGAtoPC.opt
.................\.........\save_FPGAtoPC.plg
.................\.........\SendPctoFPGA.cpp
.................\.........\SendPctoFPGA.dsp
.................\.........\SendPctoFPGA.opt
.................\.........\SendPctoFPGA.plg
.................\.........\text_02.raw
.................\.........\text_02.raw.bak
.................\.........\RAW\2D1L
.................\.........\...\2D2L
.................\.........\Debug
.................\.........\RAW
.................\2Ddwt_ALL
DWT的Verilog code