文件名称:Verilog-example
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Verilog 编程事例，8个章节，详细介绍-Verilog example
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下载文件列表
范例程序\第七章\compare16\compare16.v
........\......\compare16
........\......\decod8_fcn\decod_fcn.v
........\......\decod8_fcn
........\......\.mux14_fcn\dmux14_fcn.v
........\......\dmux14_fcn
........\......\even16_fun_fun\even16_fun_fun.v
........\......\even16_fun_fun
........\......\...._parity_16\even_parity_16.v
........\......\even_parity_16
........\......\odd_parity_16\odd_parity_16.v
........\......\odd_parity_16
........\......\shift_fcn\shift_fcn.v
........\......\shift_fcn
........\第七章
........\..五章\adder4\adder4.v
........\......\adder4
........\......\BIT_OP\bit_op.v
........\......\BIT_OP
........\......\decod3_8\decod3_8.v
........\......\decod3_8
........\......\..mul1_4\demul1_4.v
........\......\demul1_4
........\......\DIVID_8\divid_8.v
........\......\DIVID_8
........\......\encod4_2\encod4_2.v
........\......\encod4_2
........\......\EQU_INEQU\equ_inequ.v
........\......\EQU_INEQU
........\......\.VEN_PARITY\even_parity.v
........\......\EVEN_PARITY
........\......\fadd1_df\fadd1_df.v
........\......\fadd1_df
........\......\HALF_ADD\half_add.v
........\......\HALF_ADD
........\......\major\major.v
........\......\major
........\......\.ul2_1_4bits\mul2_1_4bits.v
........\......\mul2_1_4bits
........\......\sht_l_r\sht_r_l.v
........\......\sht_l_r
........\第五章
........\..八章\MEALY_BIN1\MEALY_BIN1.v
........\......\..........\MEALY_BIN1_tw.tf
........\......\MEALY_BIN1
........\......\......GRY1\MEALY_GRY1.v
........\......\..........\MEALY_GRY1_tw.tf
........\......\MEALY_GRY1
........\......\.........2\MEALY_GRY2.v
........\......\..........\MEALY_GRY2_tw.tf
........\......\MEALY_GRY2
........\......\.........3\MEALY_GRY3.v
........\......\..........\MEALY_GRY3_tw.tf
........\......\MEALY_GRY3
........\......\.OORE_BIN1\MOORE_BIN1.v
........\......\..........\MOORE_BIN1_tw.tf
........\......\MOORE_BIN1
........\......\.........2\MOORE_BIN2.v
........\......\..........\MOORE_BIN2_tw.tf
........\......\MOORE_BIN2
........\......\......ONEH1\MOORE_ONE1_tw.tf
........\......\...........\MOORE_ONEH1.v
........\......\MOORE_ONEH1
........\第八章
........\..六章\adder8_for\adder8_for.v
........\......\..........\adder8_for_tb.tf
........\......\adder8_for
........\......\BCDadder4\adder4.v
........\......\.........\BCDadder4.v
........\......\.........\BCDadder4_tb.tf
........\......\BCDadder4
........\......\bin2gra\bin2gra.v
........\......\.......\bin2gra_tb.tf
........\......\bin2gra
........\......\cnt99\cnt99_tb.tf
........\......\.....\cnt_10.V
........\......\.....\counter.V
........\......\cnt99
........\......\.omp4_if\comp4_if.v
........\......\........\comp4_if_tb.tf
........\......\comp4_if
........\......\..unter_sim\counter_sim.v
........\......\...........\counter_simtb.tf
........\......\counter_sim
........\......\....._0s\count_0s.v
........\......\count_0s
........\......\demul1_4_if\demul1_4_if.v
........\......\...........\demul1_4_if_tb.tf
........\......\demul1_4_if
........\......\encod8_3_casez\encod8_3_casex.v
........\......\..............\encod8_3_casex_tb.tf
........\......\encod8_3_casez
........\......\first_0\first_0.v
........\......\.......\first_0_tb.tf
........\......\first_0
........\......\gra2bin\gra2bin.v
........\......\.......\gra2bin_tb.tf
........\......\gra2bin
........\......\latch4_if\latch4_if.v
........\......\latch4_if