文件名称:cetvrtak13
介绍说明－－下载内容均来自于网络，请自行研究使用
8通道示波器，采用DE2-115FPGA综合，带有RS232连接，VGA驱动，IR驱动。用verilog编写。-8-channel oscilloscope, using DE2-115FPGA integrated with RS232 connection, VGA driver, IR driver. Written in verilog.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
cetvrtak13\baud_select.sv
..........\cetvrtak13.asm.rpt
..........\cetvrtak13.cdf
..........\cetvrtak13.done
..........\cetvrtak13.fit.rpt
..........\cetvrtak13.fit.smsg
..........\cetvrtak13.fit.summary
..........\cetvrtak13.flow.rpt
..........\cetvrtak13.htm
..........\cetvrtak13.jdi
..........\cetvrtak13.map.rpt
..........\cetvrtak13.map.smsg
..........\cetvrtak13.map.summary
..........\cetvrtak13.pin
..........\cetvrtak13.qpf
..........\cetvrtak13.qsf
..........\cetvrtak13.qws
..........\cetvrtak13.sdc
..........\cetvrtak13.sof
..........\cetvrtak13.sta.rpt
..........\cetvrtak13.sta.summary
..........\cetvrtak13.sv
..........\cetvrtak13.v
..........\cetvrtak13_assignment_defaults.qdf
..........\counter.sv
..........\diff.sv
..........\display.v
..........\ir_ctrl.sv
..........\IR_RECEIVE_Terasic.v
..........\maxvalue.sv
..........\minvalue.sv
..........\pc_fpga_controller.sv
..........\pc_fpga_controller.sv.bak
..........\pll.v
..........\pll1.v
..........\pll40.v
..........\PLLJ_PLLSPE_INFO.txt
..........\RAM.v
..........\ram_control.v
..........\ram_sw.v
..........\read_write_control.v
..........\receive_uart.sv
..........\register.sv
..........\rmsvalue.sv
..........\sampling.sv
..........\SEG_HEX.v
..........\send_uart.sv
..........\SPI_RX.sv
..........\sync_module.v
..........\timeScaling.sv
..........\voltageScaling.sv