文件名称:VerilogHDL_DC_Motor_control
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采用Verilog HDL语言编写的直流电动机控制系统，主要完成直流电动机的速度控制，典型的三闭环(位置、转速和电流反馈)直流电机控制系统，对控制类相关的学习者价值很高
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压缩包 : 61549822veriloghdl_dc_motor_control.rar 列表 VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\cmp_state.ini VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\Data_drive.asm.rpt VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\Data_drive.bsf VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\Data_drive.done VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\Data_drive.fit.eqn VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\Data_drive.fit.rpt VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\Data_drive.fit.summary VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\Data_drive.flow.rpt VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\Data_drive.map.eqn VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\Data_drive.map.rpt VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\Data_drive.map.summary VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\Data_drive.pin VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\Data_drive.pof VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\Data_drive.qpf VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\Data_drive.qsf VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\Data_drive.qws VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\Data_drive.sim.rpt VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\Data_drive.sof VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\Data_drive.tan.rpt VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\Data_drive.tan.summary VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\Data_drive.v VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\Data_drive.vwf VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\add_sub_mlh.tdf VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.(0).cnf.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.(0).cnf.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.(1).cnf.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.(1).cnf.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.(2).cnf.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.(2).cnf.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.(3).cnf.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.(3).cnf.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.(4).cnf.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.(4).cnf.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.(5).cnf.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.(5).cnf.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.(6).cnf.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.(6).cnf.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.(7).cnf.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.(7).cnf.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.(8).cnf.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.(8).cnf.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.asm.qmsg VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.cmp.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.cmp.ddb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.cmp.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.cmp.rdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.cmp.tdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.cmp0.ddb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.db_info VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.eco.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.eds_overflow VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.fit.qmsg VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.hier_info VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.hif VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.map.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.map.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.map.qmsg VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.pre_map.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.pre_map.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.psp VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.rtlv.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.rtlv_sg.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.rtlv_sg_swap.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.sgdiff.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.sgdiff.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.sim.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.sim.qmsg VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.sim.rdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.sim.vwf VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.sld_design_entry.sci VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.sld_design_entry_dsc.sci VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.syn_hier_info VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive.tan.qmsg VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive_cmp.qrpt VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db\Data_drive_sim.qrpt VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\cmp_state.ini VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\Data_Read.asm.rpt VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\Data_Read.bsf VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\Data_Read.done VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\Data_Read.fit.eqn VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\Data_Read.fit.rpt VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\Data_Read.fit.summary VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\Data_Read.flow.rpt VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\Data_Read.map.eqn VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\Data_Read.map.rpt VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\Data_Read.map.summary VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\Data_Read.pin VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\Data_Read.pof VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\Data_Read.qpf VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\Data_Read.qsf VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\Data_Read.qws VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\Data_Read.sim.rpt VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\Data_Read.sof VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\Data_Read.tan.rpt VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\Data_Read.tan.summary VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\Data_Read.v VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\Data_Read.vwf VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.(0).cnf.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.(0).cnf.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.(1).cnf.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.(1).cnf.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.(2).cnf.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.(2).cnf.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.(3).cnf.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.(3).cnf.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.(4).cnf.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.(4).cnf.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.asm.qmsg VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.cmp.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.cmp.ddb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.cmp.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.cmp.rdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.cmp.tdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.cmp0.ddb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.db_info VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.eco.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.eds_overflow VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.fit.qmsg VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.hier_info VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.hif VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.map.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.map.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.map.qmsg VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.pre_map.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.pre_map.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.psp VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.rtlv.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.rtlv_sg.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.rtlv_sg_swap.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.sgdiff.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.sgdiff.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.sim.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.sim.qmsg VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.sim.rdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.sim.vwf VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.sld_design_entry.sci VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.sld_design_entry_dsc.sci VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.syn_hier_info VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read.tan.qmsg VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read_cmp.qrpt VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db\Data_Read_sim.qrpt VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\cmp_state.ini VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\Data_drive.v VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\Data_Read.v VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\add_sub_mlh.tdf VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.(0).cnf.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.(0).cnf.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.(1).cnf.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.(1).cnf.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.(10).cnf.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.(10).cnf.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.(11).cnf.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.(11).cnf.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.(2).cnf.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.(2).cnf.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.(3).cnf.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.(3).cnf.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.(4).cnf.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.(4).cnf.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.(5).cnf.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.(5).cnf.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.(6).cnf.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.(6).cnf.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.(7).cnf.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.(7).cnf.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.(8).cnf.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.(8).cnf.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.(9).cnf.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.(9).cnf.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.asm.qmsg VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.cmp.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.cmp.ddb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.cmp.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.cmp.rdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.cmp.tdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.cmp0.ddb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.db_info VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.eco.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.eds_overflow VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.fit.qmsg VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.hier_info VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.hif VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.map.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.map.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.map.qmsg VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.pre_map.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.pre_map.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.psp VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.rtlv.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.rtlv_sg.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.rtlv_sg_swap.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.sgdiff.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.sgdiff.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.sim.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.sim.qmsg VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.sim.rdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.sim.vwf VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.sld_design_entry.sci VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.sld_design_entry_dsc.sci VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.syn_hier_info VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main.tan.qmsg VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main_cmp.qrpt VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db\main_sim.qrpt VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\main.asm.rpt VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\main.bdf VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\main.bsf VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\main.done VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\main.fit.eqn VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\main.fit.rpt VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\main.fit.summary VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\main.flow.rpt VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\main.map.eqn VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\main.map.rpt VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\main.map.summary VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\main.pin VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\main.pof VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\main.qpf VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\main.qsf VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\main.qws VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\main.sim.rpt VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\main.sof VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\main.tan.rpt VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\main.tan.summary VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\main.v VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\main.vwf VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\Sample_Ctrl.v VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\serv_req_info.txt VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\cmp_state.ini VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.(0).cnf.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.(0).cnf.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.asm.qmsg VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.cmp.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.cmp.ddb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.cmp.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.cmp.rdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.cmp.tdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.cmp0.ddb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.db_info VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.eco.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.eds_overflow VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.fit.qmsg VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.hier_info VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.hif VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.map.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.map.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.map.qmsg VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.pre_map.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.pre_map.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.psp VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.rtlv.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.rtlv_sg.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.rtlv_sg_swap.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.sgdiff.cdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.sgdiff.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.sim.hdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.sim.qmsg VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.sim.rdb VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.sim.vwf VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.sld_design_entry.sci VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.sld_design_entry_dsc.sci VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.syn_hier_info VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl.tan.qmsg VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl_cmp.qrpt VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db\Sample_Ctrl_sim.qrpt VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\Sample_Ctrl.asm.rpt VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\Sample_Ctrl.bsf VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\Sample_Ctrl.done VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\Sample_Ctrl.fit.eqn VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\Sample_Ctrl.fit.rpt VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\Sample_Ctrl.fit.summary VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\Sample_Ctrl.flow.rpt VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\Sample_Ctrl.map.eqn VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\Sample_Ctrl.map.rpt VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\Sample_Ctrl.map.summary VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\Sample_Ctrl.pin VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\Sample_Ctrl.pof VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\Sample_Ctrl.qpf VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\Sample_Ctrl.qsf VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\Sample_Ctrl.qws VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\Sample_Ctrl.sim.rpt VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\Sample_Ctrl.sof VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\Sample_Ctrl.tan.rpt VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\Sample_Ctrl.tan.summary VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\Sample_Ctrl.v VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\Sample_Ctrl.vwf VerilogHDL_DC_Motor_control\Current_Adjust\cmp_state.ini VerilogHDL_DC_Motor_control\Current_Adjust\Current_Adjust.asm.rpt VerilogHDL_DC_Motor_control\Current_Adjust\Current_Adjust.bsf VerilogHDL_DC_Motor_control\Current_Adjust\Current_Adjust.done VerilogHDL_DC_Motor_control\Current_Adjust\Current_Adjust.fit.eqn VerilogHDL_DC_Motor_control\Current_Adjust\Current_Adjust.fit.rpt VerilogHDL_DC_Motor_control\Current_Adjust\Current_Adjust.fit.summary VerilogHDL_DC_Motor_control\Current_Adjust\Current_Adjust.flow.rpt VerilogHDL_DC_Motor_control\Current_Adjust\Current_Adjust.map.eqn VerilogHDL_DC_Motor_control\Current_Adjust\Current_Adjust.map.rpt VerilogHDL_DC_Motor_control\Current_Adjust\Current_Adjust.map.summary VerilogHDL_DC_Motor_control\Current_Adjust\Current_Adjust.pin VerilogHDL_DC_Motor_control\Current_Adjust\Current_Adjust.pof VerilogHDL_DC_Motor_control\Current_Adjust\Current_Adjust.qpf VerilogHDL_DC_Motor_control\Current_Adjust\Current_Adjust.qsf VerilogHDL_DC_Motor_control\Current_Adjust\Current_Adjust.qws VerilogHDL_DC_Motor_control\Current_Adjust\Current_Adjust.sim.rpt VerilogHDL_DC_Motor_control\Current_Adjust\Current_Adjust.sof VerilogHDL_DC_Motor_control\Current_Adjust\Current_Adjust.tan.rpt VerilogHDL_DC_Motor_control\Current_Adjust\Current_Adjust.tan.summary VerilogHDL_DC_Motor_control\Current_Adjust\Current_Adjust.v VerilogHDL_DC_Motor_control\Current_Adjust\Current_Adjust.vwf VerilogHDL_DC_Motor_control\Current_Adjust\db\add_sub_3nh.tdf VerilogHDL_DC_Motor_control\Current_Adjust\db\add_sub_gjh.tdf VerilogHDL_DC_Motor_control\Current_Adjust\db\add_sub_jlh.tdf VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.(0).cnf.cdb VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.(0).cnf.hdb VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.asm.qmsg VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.cmp.cdb VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.cmp.ddb VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.cmp.hdb VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.cmp.rdb VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.cmp.tdb VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.cmp0.ddb VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.db_info VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.eco.cdb VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.eds_overflow VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.fit.qmsg VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.hier_info VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.hif VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.map.cdb VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.map.hdb VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.map.qmsg VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.pre_map.cdb VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.pre_map.hdb VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.psp VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.rtlv.hdb VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.rtlv_sg.cdb VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.rtlv_sg_swap.cdb VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.sgdiff.cdb VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.sgdiff.hdb VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.sim.hdb VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.sim.qmsg VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.sim.rdb VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.sim.vwf VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.sld_design_entry.sci VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.sld_design_entry_dsc.sci VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.syn_hier_info VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust.tan.qmsg VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust_cmp.qrpt VerilogHDL_DC_Motor_control\Current_Adjust\db\Current_Adjust_sim.qrpt VerilogHDL_DC_Motor_control\DC_Motor_Main\cmp_state.ini VerilogHDL_DC_Motor_control\DC_Motor_Main\Current_Adjust.v VerilogHDL_DC_Motor_control\DC_Motor_Main\Data_drive.v VerilogHDL_DC_Motor_control\DC_Motor_Main\Data_Read.v VerilogHDL_DC_Motor_control\DC_Motor_Main\db\add_sub_mlh.tdf VerilogHDL_DC_Motor_control\DC_Motor_Main\db\add_sub_pnh.tdf VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(0).cnf.cdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(0).cnf.hdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(1).cnf.cdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(1).cnf.hdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(10).cnf.cdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(10).cnf.hdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(11).cnf.cdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(11).cnf.hdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(12).cnf.cdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(12).cnf.hdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(13).cnf.cdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(13).cnf.hdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(14).cnf.cdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(14).cnf.hdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(15).cnf.cdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(15).cnf.hdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(16).cnf.cdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(16).cnf.hdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(17).cnf.cdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(17).cnf.hdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(18).cnf.cdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(18).cnf.hdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(19).cnf.cdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(19).cnf.hdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(2).cnf.cdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(2).cnf.hdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(20).cnf.cdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(20).cnf.hdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(21).cnf.cdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(21).cnf.hdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(3).cnf.cdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(3).cnf.hdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(4).cnf.cdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(4).cnf.hdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(5).cnf.cdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(5).cnf.hdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(6).cnf.cdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(6).cnf.hdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(7).cnf.cdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(7).cnf.hdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(8).cnf.cdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(8).cnf.hdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(9).cnf.cdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.(9).cnf.hdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.asm.qmsg VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.cmp.cdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.cmp.ddb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.cmp.hdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.cmp.rdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.cmp.tdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.cmp0.ddb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.db_info VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.eco.cdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.eds_overflow VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.fit.qmsg VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.hier_info VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.hif VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.map.cdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.map.hdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.map.qmsg VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.pre_map.cdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.pre_map.hdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.psp VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.rtlv.hdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.rtlv_sg.cdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.rtlv_sg_swap.cdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.sgdiff.cdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.sgdiff.hdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.sim.hdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.sim.qmsg VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.sim.rdb VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.sim.vwf VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.sld_design_entry.sci VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.sld_design_entry_dsc.sci VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.syn_hier_info VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main.tan.qmsg VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main_cmp.qrpt VerilogHDL_DC_Motor_control\DC_Motor_Main\db\DC_Motor_Main_sim.qrpt VerilogHDL_DC_Motor_control\DC_Motor_Main\DC_Motor_Main.asm.rpt VerilogHDL_DC_Motor_control\DC_Motor_Main\DC_Motor_Main.bdf VerilogHDL_DC_Motor_control\DC_Motor_Main\DC_Motor_Main.bsf VerilogHDL_DC_Motor_control\DC_Motor_Main\DC_Motor_Main.done VerilogHDL_DC_Motor_control\DC_Motor_Main\DC_Motor_Main.fit.eqn VerilogHDL_DC_Motor_control\DC_Motor_Main\DC_Motor_Main.fit.rpt VerilogHDL_DC_Motor_control\DC_Motor_Main\DC_Motor_Main.fit.summary VerilogHDL_DC_Motor_control\DC_Motor_Main\DC_Motor_Main.flow.rpt VerilogHDL_DC_Motor_control\DC_Motor_Main\DC_Motor_Main.map.eqn VerilogHDL_DC_Motor_control\DC_Motor_Main\DC_Motor_Main.map.rpt VerilogHDL_DC_Motor_control\DC_Motor_Main\DC_Motor_Main.map.summary VerilogHDL_DC_Motor_control\DC_Motor_Main\DC_Motor_Main.pin VerilogHDL_DC_Motor_control\DC_Motor_Main\DC_Motor_Main.pof VerilogHDL_DC_Motor_control\DC_Motor_Main\DC_Motor_Main.qpf VerilogHDL_DC_Motor_control\DC_Motor_Main\DC_Motor_Main.qsf VerilogHDL_DC_Motor_control\DC_Motor_Main\DC_Motor_Main.qws VerilogHDL_DC_Motor_control\DC_Motor_Main\DC_Motor_Main.sim.rpt VerilogHDL_DC_Motor_control\DC_Motor_Main\DC_Motor_Main.sof VerilogHDL_DC_Motor_control\DC_Motor_Main\DC_Motor_Main.tan.rpt VerilogHDL_DC_Motor_control\DC_Motor_Main\DC_Motor_Main.tan.summary VerilogHDL_DC_Motor_control\DC_Motor_Main\DC_Motor_Main.v VerilogHDL_DC_Motor_control\DC_Motor_Main\DC_Motor_Main.vwf VerilogHDL_DC_Motor_control\DC_Motor_Main\main.v VerilogHDL_DC_Motor_control\DC_Motor_Main\Main_Ctrl.v VerilogHDL_DC_Motor_control\DC_Motor_Main\Position_adc_ctrl.v VerilogHDL_DC_Motor_control\DC_Motor_Main\Position_Adjust.v VerilogHDL_DC_Motor_control\DC_Motor_Main\Rate_Adjust.v VerilogHDL_DC_Motor_control\DC_Motor_Main\Rate_Measure.v VerilogHDL_DC_Motor_control\DC_Motor_Main\Sample_Ctrl.v VerilogHDL_DC_Motor_control\Main\cmp_state.ini VerilogHDL_DC_Motor_control\Main\Data_drive.v VerilogHDL_DC_Motor_control\Main\Data_Read.v VerilogHDL_DC_Motor_control\Main\db\Main.db_info VerilogHDL_DC_Motor_control\Main\db\Main.eco.cdb VerilogHDL_DC_Motor_control\Main\db\Main.sld_design_entry.sci VerilogHDL_DC_Motor_control\Main\Main.bdf VerilogHDL_DC_Motor_control\Main\Main.qpf VerilogHDL_DC_Motor_control\Main\Main.qsf VerilogHDL_DC_Motor_control\Main\Main.qws VerilogHDL_DC_Motor_control\Main\main.v VerilogHDL_DC_Motor_control\Main\Position_Adjust.v VerilogHDL_DC_Motor_control\Main_Ctrl\cmp_state.ini VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.(0).cnf.cdb VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.(0).cnf.hdb VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.asm.qmsg VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.cmp.cdb VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.cmp.ddb VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.cmp.hdb VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.cmp.rdb VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.cmp.tdb VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.cmp0.ddb VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.db_info VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.eco.cdb VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.eds_overflow VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.fit.qmsg VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.hier_info VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.hif VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.map.cdb VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.map.hdb VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.map.qmsg VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.pre_map.cdb VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.pre_map.hdb VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.psp VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.rtlv.hdb VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.rtlv_sg.cdb VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.rtlv_sg_swap.cdb VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.sgdiff.cdb VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.sgdiff.hdb VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.sim.hdb VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.sim.qmsg VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.sim.rdb VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.sim.vwf VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.sld_design_entry.sci VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.sld_design_entry_dsc.sci VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.syn_hier_info VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl.tan.qmsg VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl_cmp.qrpt VerilogHDL_DC_Motor_control\Main_Ctrl\db\Main_Ctrl_sim.qrpt VerilogHDL_DC_Motor_control\Main_Ctrl\Main_Ctrl.asm.rpt VerilogHDL_DC_Motor_control\Main_Ctrl\Main_Ctrl.bsf VerilogHDL_DC_Motor_control\Main_Ctrl\Main_Ctrl.done VerilogHDL_DC_Motor_control\Main_Ctrl\Main_Ctrl.fit.eqn VerilogHDL_DC_Motor_control\Main_Ctrl\Main_Ctrl.fit.rpt VerilogHDL_DC_Motor_control\Main_Ctrl\Main_Ctrl.fit.summary VerilogHDL_DC_Motor_control\Main_Ctrl\Main_Ctrl.flow.rpt VerilogHDL_DC_Motor_control\Main_Ctrl\Main_Ctrl.map.eqn VerilogHDL_DC_Motor_control\Main_Ctrl\Main_Ctrl.map.rpt VerilogHDL_DC_Motor_control\Main_Ctrl\Main_Ctrl.map.summary VerilogHDL_DC_Motor_control\Main_Ctrl\Main_Ctrl.pin VerilogHDL_DC_Motor_control\Main_Ctrl\Main_Ctrl.pof VerilogHDL_DC_Motor_control\Main_Ctrl\Main_Ctrl.qpf VerilogHDL_DC_Motor_control\Main_Ctrl\Main_Ctrl.qsf VerilogHDL_DC_Motor_control\Main_Ctrl\Main_Ctrl.qws VerilogHDL_DC_Motor_control\Main_Ctrl\Main_Ctrl.sim.rpt VerilogHDL_DC_Motor_control\Main_Ctrl\Main_Ctrl.tan.rpt VerilogHDL_DC_Motor_control\Main_Ctrl\Main_Ctrl.tan.summary VerilogHDL_DC_Motor_control\Main_Ctrl\Main_Ctrl.v VerilogHDL_DC_Motor_control\Main_Ctrl\Main_Ctrl.vwf VerilogHDL_DC_Motor_control\Position_adc_ctrl\cmp_state.ini VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.(0).cnf.cdb VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.(0).cnf.hdb VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.asm.qmsg VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.cmp.cdb VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.cmp.ddb VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.cmp.hdb VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.cmp.rdb VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.cmp.tdb VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.cmp0.ddb VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.db_info VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.eco.cdb VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.eds_overflow VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.fit.qmsg VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.hier_info VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.hif VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.map.cdb VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.map.hdb VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.map.qmsg VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.pre_map.cdb VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.pre_map.hdb VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.psp VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.rtlv.hdb VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.rtlv_sg.cdb VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.rtlv_sg_swap.cdb VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.sgdiff.cdb VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.sgdiff.hdb VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.sim.hdb VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.sim.qmsg VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.sim.rdb VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.sim.vwf VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.sld_design_entry.sci VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.sld_design_entry_dsc.sci VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.syn_hier_info VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl.tan.qmsg VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl_cmp.qrpt VerilogHDL_DC_Motor_control\Position_adc_ctrl\db\Position_adc_ctrl_sim.qrpt VerilogHDL_DC_Motor_control\Position_adc_ctrl\Position_adc_ctrl.asm.rpt VerilogHDL_DC_Motor_control\Position_adc_ctrl\Position_adc_ctrl.bsf VerilogHDL_DC_Motor_control\Position_adc_ctrl\Position_adc_ctrl.done VerilogHDL_DC_Motor_control\Position_adc_ctrl\Position_adc_ctrl.fit.eqn VerilogHDL_DC_Motor_control\Position_adc_ctrl\Position_adc_ctrl.fit.rpt VerilogHDL_DC_Motor_control\Position_adc_ctrl\Position_adc_ctrl.fit.summary VerilogHDL_DC_Motor_control\Position_adc_ctrl\Position_adc_ctrl.flow.rpt VerilogHDL_DC_Motor_control\Position_adc_ctrl\Position_adc_ctrl.map.eqn VerilogHDL_DC_Motor_control\Position_adc_ctrl\Position_adc_ctrl.map.rpt VerilogHDL_DC_Motor_control\Position_adc_ctrl\Position_adc_ctrl.map.summary VerilogHDL_DC_Motor_control\Position_adc_ctrl\Position_adc_ctrl.pin VerilogHDL_DC_Motor_control\Position_adc_ctrl\Position_adc_ctrl.pof VerilogHDL_DC_Motor_control\Position_adc_ctrl\Position_adc_ctrl.qpf VerilogHDL_DC_Motor_control\Position_adc_ctrl\Position_adc_ctrl.qsf VerilogHDL_DC_Motor_control\Position_adc_ctrl\Position_adc_ctrl.qws VerilogHDL_DC_Motor_control\Position_adc_ctrl\Position_adc_ctrl.sim.rpt VerilogHDL_DC_Motor_control\Position_adc_ctrl\Position_adc_ctrl.sof VerilogHDL_DC_Motor_control\Position_adc_ctrl\Position_adc_ctrl.tan.rpt VerilogHDL_DC_Motor_control\Position_adc_ctrl\Position_adc_ctrl.tan.summary VerilogHDL_DC_Motor_control\Position_adc_ctrl\Position_adc_ctrl.v VerilogHDL_DC_Motor_control\Position_adc_ctrl\Position_adc_ctrl.vwf VerilogHDL_DC_Motor_control\Position_Adjust\cmp_state.ini VerilogHDL_DC_Motor_control\Position_Adjust\db\add_sub_jlh.tdf VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.(0).cnf.cdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.(0).cnf.hdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.(1).cnf.cdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.(1).cnf.hdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.(2).cnf.cdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.(2).cnf.hdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.(3).cnf.cdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.(3).cnf.hdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.(4).cnf.cdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.(4).cnf.hdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.(5).cnf.cdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.(5).cnf.hdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.(6).cnf.cdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.(6).cnf.hdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.(7).cnf.cdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.(7).cnf.hdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.(8).cnf.cdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.(8).cnf.hdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.asm.qmsg VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.cmp.cdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.cmp.ddb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.cmp.hdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.cmp.rdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.cmp.tdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.cmp0.ddb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.db_info VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.eco.cdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.eds_overflow VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.fit.qmsg VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.hier_info VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.hif VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.map.cdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.map.hdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.map.qmsg VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.pre_map.cdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.pre_map.hdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.psp VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.rtlv.hdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.rtlv_sg.cdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.rtlv_sg_swap.cdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.sgdiff.cdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.sgdiff.hdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.sim.hdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.sim.qmsg VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.sim.rdb VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.sim.vwf VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.sld_design_entry.sci VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.sld_design_entry_dsc.sci VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.syn_hier_info VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust.tan.qmsg VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust_cmp.qrpt VerilogHDL_DC_Motor_control\Position_Adjust\db\Position_Adjust_sim.qrpt VerilogHDL_DC_Motor_control\Position_Adjust\Position_Adjust.asm.rpt VerilogHDL_DC_Motor_control\Position_Adjust\Position_Adjust.bsf VerilogHDL_DC_Motor_control\Position_Adjust\Position_Adjust.done VerilogHDL_DC_Motor_control\Position_Adjust\Position_Adjust.fit.eqn VerilogHDL_DC_Motor_control\Position_Adjust\Position_Adjust.fit.rpt VerilogHDL_DC_Motor_control\Position_Adjust\Position_Adjust.fit.summary VerilogHDL_DC_Motor_control\Position_Adjust\Position_Adjust.flow.rpt VerilogHDL_DC_Motor_control\Position_Adjust\Position_Adjust.map.eqn VerilogHDL_DC_Motor_control\Position_Adjust\Position_Adjust.map.rpt VerilogHDL_DC_Motor_control\Position_Adjust\Position_Adjust.map.summary VerilogHDL_DC_Motor_control\Position_Adjust\Position_Adjust.pin VerilogHDL_DC_Motor_control\Position_Adjust\Position_Adjust.pof VerilogHDL_DC_Motor_control\Position_Adjust\Position_Adjust.qpf VerilogHDL_DC_Motor_control\Position_Adjust\Position_Adjust.qsf VerilogHDL_DC_Motor_control\Position_Adjust\Position_Adjust.qws VerilogHDL_DC_Motor_control\Position_Adjust\Position_Adjust.sim.rpt VerilogHDL_DC_Motor_control\Position_Adjust\Position_Adjust.tan.rpt VerilogHDL_DC_Motor_control\Position_Adjust\Position_Adjust.tan.summary VerilogHDL_DC_Motor_control\Position_Adjust\Position_Adjust.v VerilogHDL_DC_Motor_control\Position_Adjust\Position_Adjust.vwf VerilogHDL_DC_Motor_control\Rate_Adjust\cmp_state.ini VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.(0).cnf.cdb VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.(0).cnf.hdb VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.asm.qmsg VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.cmp.cdb VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.cmp.ddb VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.cmp.hdb VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.cmp.rdb VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.cmp.tdb VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.cmp0.ddb VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.db_info VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.eco.cdb VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.eds_overflow VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.fit.qmsg VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.hier_info VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.hif VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.map.cdb VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.map.hdb VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.map.qmsg VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.pre_map.cdb VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.pre_map.hdb VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.psp VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.rtlv.hdb VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.rtlv_sg.cdb VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.rtlv_sg_swap.cdb VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.sgdiff.cdb VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.sgdiff.hdb VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.sim.hdb VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.sim.qmsg VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.sim.rdb VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.sim.vwf VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.sld_design_entry.sci VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.sld_design_entry_dsc.sci VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.syn_hier_info VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust.tan.qmsg VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust_cmp.qrpt VerilogHDL_DC_Motor_control\Rate_Adjust\db\Rate_Adjust_sim.qrpt VerilogHDL_DC_Motor_control\Rate_Adjust\Rate_Adjust.asm.rpt VerilogHDL_DC_Motor_control\Rate_Adjust\Rate_Adjust.bsf VerilogHDL_DC_Motor_control\Rate_Adjust\Rate_Adjust.done VerilogHDL_DC_Motor_control\Rate_Adjust\Rate_Adjust.fit.eqn VerilogHDL_DC_Motor_control\Rate_Adjust\Rate_Adjust.fit.rpt VerilogHDL_DC_Motor_control\Rate_Adjust\Rate_Adjust.fit.summary VerilogHDL_DC_Motor_control\Rate_Adjust\Rate_Adjust.flow.rpt VerilogHDL_DC_Motor_control\Rate_Adjust\Rate_Adjust.map.eqn VerilogHDL_DC_Motor_control\Rate_Adjust\Rate_Adjust.map.rpt VerilogHDL_DC_Motor_control\Rate_Adjust\Rate_Adjust.map.summary VerilogHDL_DC_Motor_control\Rate_Adjust\Rate_Adjust.pin VerilogHDL_DC_Motor_control\Rate_Adjust\Rate_Adjust.pof VerilogHDL_DC_Motor_control\Rate_Adjust\Rate_Adjust.qpf VerilogHDL_DC_Motor_control\Rate_Adjust\Rate_Adjust.qsf VerilogHDL_DC_Motor_control\Rate_Adjust\Rate_Adjust.qws VerilogHDL_DC_Motor_control\Rate_Adjust\Rate_Adjust.sim.rpt VerilogHDL_DC_Motor_control\Rate_Adjust\Rate_Adjust.tan.rpt VerilogHDL_DC_Motor_control\Rate_Adjust\Rate_Adjust.tan.summary VerilogHDL_DC_Motor_control\Rate_Adjust\Rate_Adjust.v VerilogHDL_DC_Motor_control\Rate_Adjust\Rate_Adjust.vwf VerilogHDL_DC_Motor_control\Rate_Measure\cmp_state.ini VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.(0).cnf.cdb VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.(0).cnf.hdb VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.(1).cnf.cdb VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.(1).cnf.hdb VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.asm.qmsg VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.cmp.cdb VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.cmp.ddb VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.cmp.hdb VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.cmp.rdb VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.cmp.tdb VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.cmp0.ddb VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.db_info VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.eco.cdb VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.eds_overflow VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.fit.qmsg VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.hier_info VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.hif VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.map.cdb VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.map.hdb VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.map.qmsg VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.pre_map.cdb VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.pre_map.hdb VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.psp VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.rtlv.hdb VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.rtlv_sg.cdb VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.rtlv_sg_swap.cdb VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.sgdiff.cdb VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.sgdiff.hdb VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.sim.hdb VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.sim.qmsg VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.sim.rdb VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.sim.vwf VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.sld_design_entry.sci VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.sld_design_entry_dsc.sci VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.syn_hier_info VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure.tan.qmsg VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure_cmp.qrpt VerilogHDL_DC_Motor_control\Rate_Measure\db\Rate_Measure_sim.qrpt VerilogHDL_DC_Motor_control\Rate_Measure\Rate_Measure.asm.rpt VerilogHDL_DC_Motor_control\Rate_Measure\Rate_Measure.bsf VerilogHDL_DC_Motor_control\Rate_Measure\Rate_Measure.done VerilogHDL_DC_Motor_control\Rate_Measure\Rate_Measure.fit.eqn VerilogHDL_DC_Motor_control\Rate_Measure\Rate_Measure.fit.rpt VerilogHDL_DC_Motor_control\Rate_Measure\Rate_Measure.fit.summary VerilogHDL_DC_Motor_control\Rate_Measure\Rate_Measure.flow.rpt VerilogHDL_DC_Motor_control\Rate_Measure\Rate_Measure.map.eqn VerilogHDL_DC_Motor_control\Rate_Measure\Rate_Measure.map.rpt VerilogHDL_DC_Motor_control\Rate_Measure\Rate_Measure.map.summary VerilogHDL_DC_Motor_control\Rate_Measure\Rate_Measure.pin VerilogHDL_DC_Motor_control\Rate_Measure\Rate_Measure.pof VerilogHDL_DC_Motor_control\Rate_Measure\Rate_Measure.qpf VerilogHDL_DC_Motor_control\Rate_Measure\Rate_Measure.qsf VerilogHDL_DC_Motor_control\Rate_Measure\Rate_Measure.qws VerilogHDL_DC_Motor_control\Rate_Measure\Rate_Measure.sim.rpt VerilogHDL_DC_Motor_control\Rate_Measure\Rate_Measure.tan.rpt VerilogHDL_DC_Motor_control\Rate_Measure\Rate_Measure.tan.summary VerilogHDL_DC_Motor_control\Rate_Measure\Rate_Measure.v VerilogHDL_DC_Motor_control\Rate_Measure\Rate_Measure.vwf VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive\db VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read\db VerilogHDL_DC_Motor_control\Current_adc_ctrl\main\db VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl\db VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_drive VerilogHDL_DC_Motor_control\Current_adc_ctrl\Data_Read VerilogHDL_DC_Motor_control\Current_adc_ctrl\main VerilogHDL_DC_Motor_control\Current_adc_ctrl\Sample_Ctrl VerilogHDL_DC_Motor_control\Current_Adjust\db VerilogHDL_DC_Motor_control\DC_Motor_Main\db VerilogHDL_DC_Motor_control\Main\db VerilogHDL_DC_Motor_control\Main_Ctrl\db VerilogHDL_DC_Motor_control\Position_adc_ctrl\db VerilogHDL_DC_Motor_control\Position_Adjust\db VerilogHDL_DC_Motor_control\Rate_Adjust\db VerilogHDL_DC_Motor_control\Rate_Measure\db VerilogHDL_DC_Motor_control\Current_adc_ctrl VerilogHDL_DC_Motor_control\Current_Adjust VerilogHDL_DC_Motor_control\DC_Motor_Main VerilogHDL_DC_Motor_control\Main VerilogHDL_DC_Motor_control\Main_Ctrl VerilogHDL_DC_Motor_control\Position_adc_ctrl VerilogHDL_DC_Motor_control\Position_Adjust VerilogHDL_DC_Motor_control\Rate_Adjust VerilogHDL_DC_Motor_control\Rate_Measure VerilogHDL_DC_Motor_control