文件名称:time
介绍说明－－下载内容均来自于网络，请自行研究使用
FPGA做的电子钟，通过定时器实现。用vhdl做的led ip核，软件实现控制显示-FPGA do electronic bell, by timer implementation. Led ip vhdl do with nuclear, software control display
(系统自动生成,下载前可以参看下载内容)
下载文件列表
time
....\.metadata
....\.........\.lock
....\.........\.log
....\.........\.plugins
....\.........\........\com.altera.nj.ui
....\.........\........\................\dialog_settings.xml
....\.........\........\org.eclipse.cdt.core
....\.........\........\....................\.log
....\.........\........\....................\hello_world_0.1395713999908.pdom
....\.........\........\....................\hello_world_0_syslib.1395713999611.pdom
....\.........\........\org.eclipse.cdt.make.core
....\.........\........\.........................\.log
....\.........\........\.........................\hello_world_0.sc
....\.........\........\.........................\hello_world_0_syslib.sc
....\.........\........\.........................\specs.c
....\.........\........\.........................\specs.cpp
....\.........\........\org.eclipse.cdt.make.ui
....\.........\........\.......................\dialog_settings.xml
....\.........\........\org.eclipse.cdt.ui
....\.........\........\..................\dialog_settings.xml
....\.........\........\org.eclipse.core.resources
....\.........\........\..........................\.history
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