文件名称:lab2
- 所属分类：
- 其他嵌入式/单片机内容
- 资源属性：
- [ASM] [源码]
- 上传时间：
- 2014-05-07
- 文件大小：
- 335kb
- 下载次数：
- 0次
- 提 供 者：
- qinyu*****
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
熟悉XUPV2P实验开发平台。熟悉掌握Verilog HDL语言并能用其建立基本
的逻辑部件在Xilinx ISE平台进行输入、编辑、调试、仿真-Familiar XUPV2P experimental development platform. Familiar with Verilog HDL language and be able to establish its basic logical components in Xilinx ISE platform for entering, editing, debugging, simulation
的逻辑部件在Xilinx ISE平台进行输入、编辑、调试、仿真-Familiar XUPV2P experimental development platform. Familiar with Verilog HDL language and be able to establish its basic logical components in Xilinx ISE platform for entering, editing, debugging, simulation
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lab2\counter\.lso
....\.......\counter.bgn
....\.......\counter.bit
....\.......\counter.bld
....\.......\counter.cel
....\.......\counter.cmd_log
....\.......\counter.drc
....\.......\counter.ipf
....\.......\counter.ise
....\.......\counter.ise_ISE_Backup
....\.......\counter.lfp
....\.......\counter.lso
....\.......\counter.ncd
....\.......\counter.ngc
....\.......\counter.ngd
....\.......\counter.ngr
....\.......\counter.ntrc_log
....\.......\counter.pad
....\.......\counter.par
....\.......\counter.pcf
....\.......\counter.prj
....\.......\counter.restore
....\.......\counter.stx
....\.......\counter.syr
....\.......\counter.twr
....\.......\counter.twx
....\.......\counter.ucf
....\.......\counter.unroutes
....\.......\counter.ut
....\.......\counter.v
....\.......\counter.xpi
....\.......\counter.xst
....\.......\counter_guide.ncd
....\.......\counter_map.map
....\.......\counter_map.mrp
....\.......\counter_map.ncd
....\.......\counter_map.ngm
....\.......\counter_pad.csv
....\.......\counter_pad.txt
....\.......\counter_prev_built.ngd
....\.......\counter_summary.html
....\.......\counter_summary.xml
....\.......\counter_tb.fdo
....\.......\counter_tb.udo
....\.......\counter_tb.v
....\.......\counter_usage.xml
....\.......\div_n.v
....\.......\transcript
....\.......\vsim.wlf
....\.......\work\counter\verilog.asm
....\.......\....\.......\_primary.dat
....\.......\....\.......\_primary.vhd
....\.......\....\......._tb\verilog.asm
....\.......\....\..........\_primary.dat
....\.......\....\..........\_primary.vhd
....\.......\....\div_n\verilog.asm
....\.......\....\.....\_primary.dat
....\.......\....\.....\_primary.vhd
....\.......\....\glbl\verilog.asm
....\.......\....\....\_primary.dat
....\.......\....\....\_primary.vhd
....\.......\....\_info
....\.......\xst\dump.xst\counter.prj\ntrc.scr
....\.......\...\work\hdllib.ref
....\.......\...\....\vlg10\counter.bin
....\.......\...\....\...38\div__n.bin
....\.......\_impact.cmd
....\.......\_impact.log
....\.......\.ngo\netlist.lst
....\.......\_pace.ucf
....\.......\.xmsgs\bitgen.xmsgs
....\.......\......\map.xmsgs
....\.......\......\ngdbuild.xmsgs
....\.......\......\par.xmsgs
....\.......\......\trce.xmsgs
....\.......\......\xst.xmsgs
....\.......\xst\dump.xst\counter.prj\ngx\notopt
....\.......\...\........\...........\...\opt
....\.......\...\........\...........\ngx
....\.......\...\........\counter.prj
....\.......\...\work\vlg10
....\.......\...\....\vlg38
....\.......\work\counter
....\.......\....\counter_tb
....\.......\....\div_n
....\.......\....\glbl
....\.......\xst\dump.xst
....\.......\...\projnav.tmp
....\.......\...\work
....\.......\work
....\.......\xst
....\.......\_ngo
....\.......\_xmsgs
....\counter
lab2