文件名称:dpll
介绍说明－－下载内容均来自于网络，请自行研究使用
用verilog编写的全数字锁相环，包括鉴相器，模K计数器，加减脉冲模块和分频模块，都经过验证-verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider
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下载文件列表
dpll\div_8.v
....\even_f.v
....\IDcounter.v
....\IDcounter_t.v
....\jk_ff.v
....\kcounter.v
....\property.sv
....\tb_dac.v
....\tb_IDcounter.v
....\tb_jk.v
....\tb_k.v
....\tb_top.v
....\test_top.sv
....\top.v
dpll