文件名称:Verilog_UART
介绍说明－－下载内容均来自于网络，请自行研究使用
the file use verilog HDL to realize uart.it contain
recive and transmit.-the files use verilog HDL to realize uart.it contain
reciver and transmitor.
recive and transmit.-the files use verilog HDL to realize uart.it contain
reciver and transmitor.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Verilog实现串口\speed_select_rx.v
...............\speed_select_tx.v
...............\uart_recive_module.v
...............\uart_transmit_module.v
Verilog实现串口