文件名称:multiply_8_VHDL
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由8 位加法器构成的以时序方式设计的8 位乘法器，采用逐项移位相加的方
法来实现相乘的VHDL程序代码。包含几个小模块和一个顶层设计文件，运行可用。-an 8 bit multiplier combined with 8 bit adder using a design by way of timing,and it use a way of Itemized shift to implement the multiply.It include some little module and a top level design document.
法来实现相乘的VHDL程序代码。包含几个小模块和一个顶层设计文件，运行可用。-an 8 bit multiplier combined with 8 bit adder using a design by way of timing,and it use a way of Itemized shift to implement the multiply.It include some little module and a top level design document.
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下载文件列表
multiply_8_VHDL\add4.vhd
...............\add8.vhd
...............\latch_16.vhd
...............\multi8.vhd
...............\mult_1.vhd
...............\mul_ctrl.vhd
...............\reg_8.vhd
multiply_8_VHDL