文件名称:clockdiv_teste
- 所属分类:
- VHDL编程
- 资源属性:
- [VHDL] [源码]
- 上传时间:
- 2014-04-11
- 文件大小:
- 577kb
- 下载次数:
- 0次
- 提 供 者:
- rafael*******
- 相关连接:
- 无
- 下载说明:
- 别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容均来自于网络,请自行研究使用
Clock division program write in Verilog with selected divider (32 bits)
(系统自动生成,下载前可以参看下载内容)
下载文件列表
clockdiv_teste\output_files\greybox_tmp\cbx_args.txt
..............\incremental_db\compiled_partitions\clockdiv_teste.db_info
..............\..............\...................\clockdiv_teste.root_partition.map.hbdb.hb_info
..............\..............\...................\clockdiv_teste.root_partition.map.kpt
..............\..............\...................\clockdiv_teste.root_partition.map.dpi
..............\..............\...................\clockdiv_teste.root_partition.map.cdb
..............\..............\...................\clockdiv_teste.root_partition.map.hdb
..............\..............\...................\clockdiv_teste.root_partition.map.hbdb.sig
..............\..............\...................\clockdiv_teste.root_partition.cmp.dfp
..............\..............\...................\clockdiv_teste.root_partition.map.hbdb.hdb
..............\..............\...................\clockdiv_teste.root_partition.cmp.logdb
..............\..............\...................\clockdiv_teste.root_partition.cmp.rcfdb
..............\..............\...................\clockdiv_teste.root_partition.cmp.cdb
..............\..............\...................\clockdiv_teste.root_partition.cmp.hdb
..............\..............\...................\clockdiv_teste.root_partition.cmp.ammdb
..............\..............\...................\clockdiv_teste.root_partition.cmp.kpt
..............\..............\...................\clockdiv_teste.root_partition.map.hbdb.cdb
..............\simulation\modelsim\clockdiv_teste_modelsim.xrf
..............\..........\........\clockdiv_teste.vho
..............\..........\........\clockdiv_teste_fast.vho
..............\..........\........\clockdiv_teste_vhd.sdo
..............\..........\........\clockdiv_teste_vhd_fast.sdo
..............\..........\........\clockdiv_teste.sft
..............\greybox_tmp\greybox_tmp\mg4h8.v
..............\db\clockdiv_teste.db_info
..............\..\clockdiv_teste.map.qmsg
..............\..\clockdiv_teste.lpc.txt
..............\..\logic_util_heursitic.dat
..............\..\clockdiv_teste.cbx.xml
..............\..\clockdiv_teste.hif
..............\..\clockdiv_teste.sld_design_entry.sci
..............\..\prev_cmp_clockdiv_teste.qmsg
..............\..\clockdiv_teste.pre_map.hdb
..............\..\clockdiv_teste.smart_action.txt
..............\..\clockdiv_teste.rtlv_sg.cdb
..............\..\clockdiv_teste.tis_db_list.ddb
..............\..\clockdiv_teste.pti_db_list.ddb
..............\..\clockdiv_teste.hier_info
..............\..\clockdiv_teste.lpc.html
..............\..\clockdiv_teste.map_bb.hdb
..............\..\clockdiv_teste.sgdiff.cdb
..............\..\clockdiv_teste.rtlv.hdb
..............\..\clockdiv_teste.rtlv_sg_swap.cdb
..............\..\clockdiv_teste.sld_design_entry_dsc.sci
..............\..\clockdiv_teste.sgdiff.hdb
..............\..\clockdiv_teste.lpc.rdb
..............\..\clockdiv_teste.map_bb.logdb
..............\..\clockdiv_teste.cmp0.ddb
..............\..\clockdiv_teste.asm.qmsg
..............\..\clockdiv_teste.syn_hier_info
..............\..\clockdiv_teste.root_partition.map.reg_db.cdb
..............\..\clockdiv_teste.sta.qmsg
..............\..\clockdiv_teste.cmp.logdb
..............\..\clockdiv_teste.map.kpt
..............\..\clockdiv_teste.map_bb.cdb
..............\..\clockdiv_teste.fit.qmsg
..............\..\clockdiv_teste.cmp_merge.kpt
..............\..\clockdiv_teste.cmp.rdb
..............\..\clockdiv_teste.cmp1.ddb
..............\..\clockdiv_teste.eda.qmsg
..............\..\clockdiv_teste.map.ammdb
..............\..\clockdiv_teste.cmp.kpt
..............\..\clockdiv_teste.routing.rdb
..............\..\clockdiv_teste.pplq.rdb
..............\..\clockdiv_teste.cmp2.ddb
..............\..\clockdiv_teste.asm.rdb
..............\..\clockdiv_teste.sta.rdb
..............\..\clockdiv_teste.cmp.hdb
..............\..\clockdiv_teste.map.logdb
..............\..\clockdiv_teste.tmw_info
..............\..\clockdiv_teste.vpr.ammdb
..............\..\clockdiv_teste.map.cdb
..............\..\clockdiv_teste.map.hdb
..............\..\clockdiv_teste.cmp.cdb
..............\