文件名称:FPGA-implementation-of-dsp
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《数字信号处理的FPGA实现》一书的源代码，包括verilog和VHDL版本。该书是算法的硬件实现的权威书籍。-" FPGA digital signal processing," a book of the source code, including verilog and VHDL versions. The book is the definitive book on the algorithm for hardware implementation.
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下载文件列表
FPGA implementation of dsp
..........................\BOOK2E
..........................\......\UTIL
..........................\......\....\93VHDL.VHD
..........................\......\....\95DIRECT.V
..........................\......\....\95KEY.V
..........................\......\....\95TASKS.V
..........................\......\....\CASE3.VHD
..........................\......\....\CASE3S.VHD
..........................\......\....\CASE5P.VHD
..........................\......\....\CIC00.DAT
..........................\......\....\CIC00.IMP
..........................\......\....\COPYRIGHT
..........................\......\....\CSD.DAT
..........................\......\....\DAROM3.MIF
..........................\......\....\DAROM5.MIF
..........................\......\....\DSP4FPGA.HTM
..........................\......\....\FPTAB05.MIF
..........................\......\....\INS-STUDENT.HTM
..........................\......\....\LCS.V
..........................\......\....\LCS.VHD
..........................\......\....\MHZ.V
..........................\......\....\MHZ.VHD
..........................\......\....\QUICKLOG.PDF
..........................\......\....\QUICKVER.PDF
..........................\......\....\QUICKVHD.PDF
..........................\......\....\SINE.MIF
..........................\......\VERILOG
..........................\......\.......\210MEM.V
..........................\......\.......\210MODEL.V
..........................\......\.......\220MODEL.V
..........................\......\.......\ADD_1P.SCF
..........................\......\.......\ADD_1P.V
..........................\......\.......\ADD_2P.HIF
..........................\......\.......\ADD_2P.SCF
..........................\......\.......\ADD_2P.V
..........................\......\.......\ADD_3P.SCF
..........................\......\.......\ADD_3P.V
..........................\......\.......\ADD_FF8.V
..........................\......\.......\ADD_FF8CIN.V
..........................\......\.......\AMMOD.SCF
..........................\......\.......\AMMOD.V
..........................\......\.......\BFPROC.SCF
..........................\......\.......\BFPROC.V
..........................\......\.......\CASE3.V
..........................\......\.......\CASE3S.V
..........................\......\.......\CASE5P.V
..........................\......\.......\CCMUL.SCF
..........................\......\.......\CCMUL.V
..........................\......\.......\CIC3R32.SCF
..........................\......\.......\CIC3R32.V
..........................\......\.......\CIC3S32.SCF
..........................\......\.......\CIC3S32.V
..........................\......\.......\CORDIC.SCF
..........................\......\.......\CORDIC.V
..........................\......\.......\CSA7.V
..........................\......\.......\CSA7CIN.V
..........................\......\.......\DAFSM.SCF
..........................\......\.......\DAFSM.V
..........................\......\.......\DAPARA.SCF
..........................\......\.......\DAPARA.V
..........................\......\.......\DAROM.SCF
..........................\......\.......\DAROM.V
..........................\......\.......\DAROM3.MIF
..........................\......\.......\DASIGN.SCF
..........................\......\.......\DASIGN.V
..........................\......\.......\DB4LATTI.SCF
..........................\......\.......\DB4LATTI.V
..........................\......\.......\DB4POLY.SCF
..........................\......\.......\DB4POLY.V
..........................\......\.......\DIV_AEGP.SCF
..........................\......\.......\DIV_AEGP.V
..........................\......\.......\DIV_RES.SCF
..........................\......\.......\DIV_RES.V
..........................\......\.......\EXAMPLE.SCF
..........................\......\.......\EXAMPLE.V
..........................\......\.......\FC2
..........................\......\.......\...\220MODEL.V
..........................\......\.......\...\ADD_1P.V
..........................\......\.......\...\ADD_2P.V
..........................\......\.......\...\A