文件名称:dtrigger

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [HTML]
  • 上传时间:
  • 2014-03-24
  • 文件大小:
  • 15.8mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • w**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

分频器,对输入时钟进行分频,可以用来驱动电机,或者用作其他需要时钟源的外设的驱动信号-Divider, devide the input clock frequency to another frequence clock signal
(系统自动生成,下载前可以参看下载内容)

下载文件列表





dtrigger\db\dtrigger.amm.cdb

........\..\dtrigger.asm.qmsg

........\..\dtrigger.asm.rdb

........\..\dtrigger.cbx.xml

........\..\dtrigger.cmp.kpt

........\..\dtrigger.cmp.rdb

........\..\dtrigger.db_info

........\..\dtrigger.eda.qmsg

........\..\dtrigger.fit.qmsg

........\..\dtrigger.hier_info

........\..\dtrigger.hif

........\..\dtrigger.idb.cdb

........\..\dtrigger.lpc.html

........\..\dtrigger.lpc.rdb

........\..\dtrigger.lpc.txt

........\..\dtrigger.map.cdb

........\..\dtrigger.map.hdb

........\..\dtrigger.map.logdb

........\..\dtrigger.map.qmsg

........\..\dtrigger.pre_map.cdb

........\..\dtrigger.pre_map.hdb

........\..\dtrigger.rtlv.hdb

........\..\dtrigger.rtlv_sg.cdb

........\..\dtrigger.rtlv_sg_swap.cdb

........\..\dtrigger.sgdiff.cdb

........\..\dtrigger.sgdiff.hdb

........\..\dtrigger.sld_design_entry.sci

........\..\dtrigger.sld_design_entry_dsc.sci

........\..\dtrigger.smart_action.txt

........\..\dtrigger.sta.qmsg

........\..\dtrigger.sta.rdb

........\..\dtrigger.syn_hier_info

........\..\dtrigger.tis_db_list.ddb

........\..\dtrigger.tmw_info

........\..\logic_util_heursitic.dat

........\..\prev_cmp_dtrigger.qmsg

........\dtrigger.asm.rpt

........\dtrigger.done

........\dtrigger.eda.rpt

........\dtrigger.fit.rpt

........\dtrigger.fit.smsg

........\dtrigger.fit.summary

........\dtrigger.flow.rpt

........\dtrigger.map.rpt

........\dtrigger.map.summary

........\dtrigger.pin

........\dtrigger.pof

........\dtrigger.qpf

........\dtrigger.qsf

........\dtrigger.sta.rpt

........\dtrigger.sta.summary

........\dtrigger.vhd

........\dtrigger.vhd.bak

........\dtrigger_nativelink_simulation.rpt

........\incremental_db\compiled_partitions\dtrigger.db_info

........\..............\...................\dtrigger.root_partition.map.kpt

........\..............\README

........\simulation\modelsim\dtrigger.vht

........\..........\........\dtrigger.vht.bak

........\..........\........\dtrigger_run_msim_rtl_vhdl.do

........\..........\........\dtrigger_run_msim_rtl_vhdl.do.bak

........\..........\........\dtrigger_run_msim_rtl_vhdl.do.bak1

........\..........\........\dtrigger_run_msim_rtl_vhdl.do.bak10

........\..........\........\dtrigger_run_msim_rtl_vhdl.do.bak11

........\..........\........\dtrigger_run_msim_rtl_vhdl.do.bak2

........\..........\........\dtrigger_run_msim_rtl_vhdl.do.bak3

........\..........\........\dtrigger_run_msim_rtl_vhdl.do.bak4

........\..........\........\dtrigger_run_msim_rtl_vhdl.do.bak5

........\..........\........\dtrigger_run_msim_rtl_vhdl.do.bak6

........\..........\........\dtrigger_run_msim_rtl_vhdl.do.bak7

........\..........\........\dtrigger_run_msim_rtl_vhdl.do.bak8

........\..........\........\dtrigger_run_msim_rtl_vhdl.do.bak9

........\..........\........\modelsim.ini

........\..........\........\msim_transcript

........\..........\........\rtl_work\dtrigger\behavior.dat

........\..........\........\........\........\behavior.dbs

........\..........\........\........\........\behavior.prw

........\..........\........\........\........\behavior.psm

........\..........\........\........\........\_primary.dat

........\..........\........\........\........\_primary.dbs

........\..........\........\........\........_vhd_tst\dtrigger_arch.dat

........\..........\........\........\................\dtrigger_arch.dbs

........\..........\........\........\................\dtrigger_arch.prw

........\..........\........\........\................\dtrigger_arch.psm

........\..........\........\........\................\_primary.dat

........\..........\........\........\................\_primary.dbs

........\..........\........\........\_info

........\..........\........\........\_vmake

........\..........\........\vish_stacktrace.vstf

........\..........\........\vsim.wlf

........\..........\........\rtl_work\dtrigger

........\..........\........\........\dtrigger_vhd_tst

........\..........\........\........\_temp

........\..........\........\rtl_work

........\incremental_db\compiled_partitions

........\simulation\modelsim

........\db

........\incremental_db

........\simulation

dtrigger

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