文件名称:zidong_led_water
介绍说明－－下载内容均来自于网络，请自行研究使用
用Verilog语言实现了将50MHz时钟分频到1Hz，实现了自动流水显示HELLO字母功能-Verilog language of the 50MHz clock frequency to 1Hz, realized the function of automatic water display HELLO letters
(系统自动生成,下载前可以参看下载内容)
下载文件列表
zidong_led_water\db\prev_cmp_zidong_led_water.asm.qmsg
................\..\prev_cmp_zidong_led_water.eda.qmsg
................\..\prev_cmp_zidong_led_water.fit.qmsg
................\..\prev_cmp_zidong_led_water.map.qmsg
................\..\prev_cmp_zidong_led_water.qmsg
................\..\prev_cmp_zidong_led_water.tan.qmsg
................\..\zidong_led_water.asm.qmsg
................\..\zidong_led_water.asm_labs.ddb
................\..\zidong_led_water.cbx.xml
................\..\zidong_led_water.cmp.bpm
................\..\zidong_led_water.cmp.cdb
................\..\zidong_led_water.cmp.ecobp
................\..\zidong_led_water.cmp.hdb
................\..\zidong_led_water.cmp.kpt
................\..\zidong_led_water.cmp.logdb
................\..\zidong_led_water.cmp.rdb
................\..\zidong_led_water.cmp.tdb
................\..\zidong_led_water.cmp0.ddb
................\..\zidong_led_water.cmp_merge.kpt
................\..\zidong_led_water.db_info
................\..\zidong_led_water.eco.cdb
................\..\zidong_led_water.eda.qmsg
................\..\zidong_led_water.fit.qmsg
................\..\zidong_led_water.hier_info
................\..\zidong_led_water.hif
................\..\zidong_led_water.lpc.html
................\..\zidong_led_water.lpc.rdb
................\..\zidong_led_water.lpc.txt
................\..\zidong_led_water.map.bpm
................\..\zidong_led_water.map.cdb
................\..\zidong_led_water.map.ecobp
................\..\zidong_led_water.map.hdb
................\..\zidong_led_water.map.kpt
................\..\zidong_led_water.map.logdb
................\..\zidong_led_water.map.qmsg
................\..\zidong_led_water.map_bb.cdb
................\..\zidong_led_water.map_bb.hdb
................\..\zidong_led_water.map_bb.logdb
................\..\zidong_led_water.pre_map.cdb
................\..\zidong_led_water.pre_map.hdb
................\..\zidong_led_water.rtlv.hdb
................\..\zidong_led_water.rtlv_sg.cdb
................\..\zidong_led_water.rtlv_sg_swap.cdb
................\..\zidong_led_water.sgdiff.cdb
................\..\zidong_led_water.sgdiff.hdb
................\..\zidong_led_water.sld_design_entry.sci
................\..\zidong_led_water.sld_design_entry_dsc.sci
................\..\zidong_led_water.syn_hier_info
................\..\zidong_led_water.tan.qmsg
................\..\zidong_led_water.tis_db_list.ddb
................\..\zidong_led_water.tmw_info
................\incremental_db\compiled_partitions\zidong_led_water.root_partition.cmp.atm
................\..............\...................\zidong_led_water.root_partition.cmp.dfp
................\..............\...................\zidong_led_water.root_partition.cmp.hdbx
................\..............\...................\zidong_led_water.root_partition.cmp.kpt
................\..............\...................\zidong_led_water.root_partition.cmp.logdb
................\..............\...................\zidong_led_water.root_partition.cmp.rcf
................\..............\...................\zidong_led_water.root_partition.map.atm
................\..............\...................\zidong_led_water.root_partition.map.dpi
................\..............\...................\zidong_led_water.root_partition.map.hdbx
................\..............\...................\zidong_led_water.root_partition.map.kpt
................\..............\README
................\simulation\modelsim\modelsim.ini
................\..........\........\msim_transcript
................\..........\........\rtl_work\zidong_led_water\verilog.prw
................\..........\........\........\................\verilog.psm
................\..........\........\........\................\_primary.dat
................\..........\........\........\................\_primary.dbs
................\..........\........\........\................\_primary.vhd
................\..........\........\........\................_vlg_tst\verilog.prw
................\..........\........\........\........................\verilog.psm
................\......