文件名称:i2c_master_slave_core
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I2C接口的主从模式代码,独立的IP，可以快速嵌入到自己的设计项目！-Master I2C interface code from the model, independent of IP, you can quickly embed into their design projects!
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下载文件列表
i2c_master_slave_core\doc\i2c_core_verification_plan.pdf
.....................\...\i2c_spec.doc
.....................\...\i2c_spec.pdf
.....................\svtb\Readme
.....................\....\vmm_svtb\config.sv
.....................\....\........\sb_callback.sv0000644
.....................\....\........\vmm_clkgen.sv
.....................\....\........\vmm_i2c_callback.sv
.....................\....\........\vmm_i2c_coverage.sv
.....................\....\........\vmm_i2c_data_packet.sv
.....................\....\........\vmm_i2c_driver.sv
.....................\....\........\vmm_i2c_env.sv0000644
.....................\....\........\vmm_i2c_interface.sv
.....................\....\........\vmm_i2c_monitor.sv
.....................\....\........\vmm_i2c_mon_pkt.sv
.....................\....\........\vmm_i2c_reg_pkt.sv
.....................\....\........\vmm_i2c_sb_pkt.sv
.....................\....\........\vmm_i2c_scenario_generator.sv
.....................\....\........\vmm_i2c_scenario_packet.sv
.....................\....\........\vmm_i2c_scoreboard.sv
.....................\....\........\vmm_i2c_slave_driver.sv
.....................\....\........\vmm_i2c_stimulus_packet.sv
.....................\....\........\vmm_i2c_top.sv0000644
.....................\....\........\vmm_program1_test.sv
.....................\....\........\vmm_program_test.sv
.....................\verilog\rtl\controller_interface.v
.....................\.......\...\controller_interface.v.bak
.....................\.......\...\counter.v
.....................\.......\...\counter.v.bak
.....................\.......\...\i2c_blk.v
.....................\.......\...\i2c_blk.v.bak
.....................\.......\...\ms_core.v
.....................\.......\...\ms_core.v.bak
.....................\.......\...\shift.v
.....................\.......\...\shift.v.bak
.....................\svtb\vmm_svtb
.....................\verilog\rtl
.....................\doc
.....................\svtb
.....................\verilog
i2c_master_slave_core