文件名称:uart_fifo
介绍说明－－下载内容均来自于网络，请自行研究使用
带fifo的串口通信verilog设计，该设计为学习uart所用，完成PC端发送至fpga后fpga原数据返回，支持长字符串。-Serial communication with fifo verilog design, which is used to learn uart complete PC sends data back to the original post fpga fpga, support long strings.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
uart_fifo\clk_gen.v
.........\clk_gen.v.bak
.........\db\altsyncram_0124.tdf
.........\..\altsyncram_1124.tdf
.........\..\altsyncram_4u14.tdf
.........\..\altsyncram_8124.tdf
.........\..\altsyncram_g124.tdf
.........\..\altsyncram_q0k1.tdf
.........\..\altsyncram_u024.tdf
.........\..\a_dpfifo_ca31.tdf
.........\..\a_fefifo_18e.tdf
.........\..\cmpr_ngc.tdf
.........\..\cmpr_qgc.tdf
.........\..\cmpr_rgc.tdf
.........\..\cntr_23j.tdf
.........\..\cntr_3ob.tdf
.........\..\cntr_agi.tdf
.........\..\cntr_bbj.tdf
.........\..\cntr_bgi.tdf
.........\..\cntr_egi.tdf
.........\..\cntr_fo7.tdf
.........\..\cntr_i6j.tdf
.........\..\cntr_igi.tdf
.........\..\cntr_kgi.tdf
.........\..\cntr_o9j.tdf
.........\..\decode_dvf.tdf
.........\..\decode_jsa.tdf
.........\..\dpram_4711.tdf
.........\..\logic_util_heursitic.dat
.........\..\mux_1tc.tdf
.........\..\mux_dob.tdf
.........\..\mux_eob.tdf
.........\..\mux_hob.tdf
.........\..\mux_ssc.tdf
.........\..\mux_vsc.tdf
.........\..\prev_cmp_uart.qmsg
.........\..\scfifo_5431.tdf
.........\..\uart.db_info
.........\fifo_rw.v
.........\fifo_rw.v.bak
.........\greybox_tmp\cbx_args.txt
.........\incremental_db\compiled_partitions\uart.db_info
.........\..............\README
.........\output_files\output_file.jic
.........\............\stp1.stp
.........\............\stp1_auto_stripped.stp
.........\............\uart.asm.rpt
.........\............\uart.cdf
.........\............\uart.done
.........\............\uart.fit.rpt
.........\............\uart.fit.smsg
.........\............\uart.fit.summary
.........\............\uart.flow.rpt
.........\............\uart.jdi
.........\............\uart.map.rpt
.........\............\uart.map.summary
.........\............\uart.pin
.........\............\uart.pof
.........\............\uart.sof
.........\............\uart.sta.rpt
.........\............\uart.sta.summary
.........\receive.v
.........\receive.v.bak
.........\send.v
.........\send.v.bak
.........\uart.qpf
.........\uart.qsf
.........\uart.qws
.........\uart.v
.........\uart.v.bak
.........\uart_assignment_defaults.qdf
.........\uar_fifo.qip
.........\uar_fifo.v
.........\uar_fifo_bb.v
.........\incremental_db\compiled_partitions
.........\db
.........\greybox_tmp
.........\incremental_db
.........\output_files
uart_fifo