文件名称:vhdl
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verilog for LVDS altera stratix4
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Nuova cartella
..............\altlvds.qpf
..............\altlvds.qsf
..............\altlvds.qws
..............\altlvds.v
..............\altlvds.v.bak
..............\altlvds_nativelink_simulation.rpt
..............\Block2.bdf
..............\Block2.v
..............\Block2.v.bak
..............\Block2_tb.v
..............\Block2_tb.v.bak
..............\loop_tb.v
..............\loop_tb.v.bak
..............\pll.bsf
..............\pll.cmp
..............\pll.inc
..............\pll.ppf
..............\pll.qip
..............\pll.v
..............\PLLJ_PLLSPE_INFO.txt
..............\pll_bb.v
..............\pll_inst.v
..............\pll_syn.v
..............\rx_lvds.bsf
..............\rx_lvds.cmp
..............\rx_lvds.inc
..............\rx_lvds.ppf
..............\rx_lvds.qip
..............\rx_lvds.v
..............\rx_lvds_bb.v
..............\rx_lvds_inst.v
..............\rx_lvds_syn.v
..............\tx_lvds.bsf
..............\tx_lvds.cmp
..............\tx_lvds.inc
..............\tx_lvds.ppf
..............\tx_lvds.qip
..............\tx_lvds.v
..............\tx_lvds_bb.v
..............\tx_lvds_inst.v
..............\tx_lvds_syn.v