文件名称:adc_ctl
介绍说明－－下载内容均来自于网络，请自行研究使用
AD采集芯片ADS8328的Verilog驱动代码，经过验证可用 -//Target IC: ADS8328(Read fr a me Controlled via CS(FS=1)
// IC Descr iption: Manual Channel Select, CLK Period = 10MHz(1MHz-21MHz), CS_n Low to DataVaild [3ns,15ns]
// IC Time Sequence: da_tick = 50ns, da work period=da_tick*20=50*20=1000ns,
// Total Period=da_tick*25(conten a da_cs_n idle)
// Convst pin low for a minimum of 40 ns, Total Acquisition+ Conversion Cycle Time >=21CCLKs
// IC Descr iption: Manual Channel Select, CLK Period = 10MHz(1MHz-21MHz), CS_n Low to DataVaild [3ns,15ns]
// IC Time Sequence: da_tick = 50ns, da work period=da_tick*20=50*20=1000ns,
// Total Period=da_tick*25(conten a da_cs_n idle)
// Convst pin low for a minimum of 40 ns, Total Acquisition+ Conversion Cycle Time >=21CCLKs
(系统自动生成,下载前可以参看下载内容)
下载文件列表
adc_ctl.v