文件名称:Chapter-5
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- 书籍源码
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- [ASM] [源码]
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- 2013-09-29
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- 366kb
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- shixi******
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5.2 16位乘法器状态机实现
5.3 交通控制灯控制设计
5.4 PCI总线目标接口状态机设计-5.2 16 5.3 multiplier state machine traffic light control design 5.4 PCI bus target interface state machine design
5.3 交通控制灯控制设计
5.4 PCI总线目标接口状态机设计-5.2 16 5.3 multiplier state machine traffic light control design 5.4 PCI bus target interface state machine design
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下载文件列表
Chapter-5\5.2\chart\Thumbs.db
.........\...\.....\图5-5.bmp
.........\...\.....\图5-6.bmp
.........\...\.....\表5-1.bmp
.........\...\mult16.cr.mti
.........\...\mult16.mpf
.........\...\multiplication.v
.........\...\multiplication_testbench.v
.........\...\transcript
.........\...\vsim.wlf
.........\...\wave\multiplication.bmp
.........\...\....\multiplication_testbench.bmp
.........\...\....\Thumbs.db
.........\...\.ork\multiplication\verilog.asm
.........\...\....\..............\_primary.dat
.........\...\....\..............\_primary.vhd
.........\...\....\.............._testbench\verilog.asm
.........\...\....\........................\_primary.dat
.........\...\....\........................\_primary.vhd
.........\...\....\_info
.........\..3\chart\Thumbs.db
.........\...\.....\图5-7.bmp
.........\...\.....\图5-9.bmp
.........\...\.....\表5-3.bmp
.........\...\.....\表5-3（续）.bmp
.........\...\traffic.cr.mti
.........\...\traffic.mpf
.........\...\traffic.v
.........\...\traffic_testbench.v
.........\...\transcript
.........\...\vsim.wlf
.........\...\wave\Thumbs.db
.........\...\....\traffic.bmp
.........\...\....\traffic_testbench.bmp
.........\...\.ork\traffic\verilog.asm
.........\...\....\.......\_primary.dat
.........\...\....\.......\_primary.vhd
.........\...\....\......._testbench\verilog.asm
.........\...\....\.................\_primary.dat
.........\...\....\.................\_primary.vhd
.........\...\....\_info
.........\..4\chart\Thumbs.db
.........\...\.....\图5-14.bmp
.........\...\.....\图5-15.bmp
.........\...\.....\表5-4(续1-1).bmp
.........\...\.....\表5-4(续1-2).bmp
.........\...\.....\表5-4(续2).bmp
.........\...\.....\表5-4.bmp
.........\...\note.txt
.........\...\pci.cr.mti
.........\...\pci.mpf
.........\...\pci_tb.v
.........\...\state_machine.v
.........\...\transcript
.........\...\vsim.wlf
.........\...\wave\pci_tb.bmp
.........\...\....\state_machine.bmp
.........\...\....\Thumbs.db
.........\...\.ork\base_addr_chk\verilog.asm
.........\...\....\.............\_primary.dat
.........\...\....\.............\_primary.vhd
.........\...\....\.kend_daemon\verilog.asm
.........\...\....\............\_primary.dat
.........\...\....\............\_primary.vhd
.........\...\....\config_mux\verilog.asm
.........\...\....\..........\_primary.dat
.........\...\....\..........\_primary.vhd
.........\...\....\glue\verilog.asm
.........\...\....\....\_primary.dat
.........\...\....\....\_primary.vhd
.........\...\....\pargen\verilog.asm
.........\...\....\......\_primary.dat
.........\...\....\......\_primary.vhd
.........\...\....\.ci_clk_reset\verilog.asm
.........\...\....\.............\_primary.dat
.........\...\....\.............\_primary.vhd
.........\...\....\....stim\verilog.asm
.........\...\....\........\_primary.dat
.........\...\....\........\_primary.vhd
.........\...\....\....tb\verilog.asm
.........\...\....\......\_primary.dat
.........\...\....\......\_primary.vhd
.........\...\....\.....op\verilog.asm
.........\...\....\.......\_primary.dat
.........\...\....\.......\_primary.vhd
.........\...\....\retry_count\verilog.asm
.........\...\....\...........\_primary.dat
.........\...\....\...........\_primary.vhd
.........\...\....\state_machine\verilog.asm
.........\...\....\.............\_primary.dat
.........\...\....\.............\_primary.vhd
.........\...\....\_info
.........\..2\work\multiplication
.........\...\....\multiplication_testbench
.........\..3\work\traffic
.........\...\....\traffic_testbench
.........\..4\work\base_addr_chk
.........\...\....\bkend_daemon
.........\...\....\config_mux
.........\...\....\glue