文件名称:verilog_EX1
介绍说明－－下载内容均来自于网络，请自行研究使用
对50MHz的信号进行2分频信号，寄存器cnt 20ms循环计数-Signals on 50MHz signal divided by 2, the loop count register cnt 20ms
(系统自动生成,下载前可以参看下载内容)
下载文件列表
verilog_EX1
...........\.sopc_builder
...........\.............\install.ptf
...........\clkdiv.asm.rpt
...........\clkdiv.cdf
...........\clkdiv.done
...........\clkdiv.dpf
...........\clkdiv.eda.rpt
...........\clkdiv.fit.rpt
...........\clkdiv.fit.smsg
...........\clkdiv.fit.summary
...........\clkdiv.flow.rpt
...........\clkdiv.map.rpt
...........\clkdiv.map.summary
...........\clkdiv.pin
...........\clkdiv.pof
...........\clkdiv.qpf
...........\clkdiv.qsf
...........\clkdiv.qws
...........\clkdiv.tan.rpt
...........\clkdiv.tan.summary
...........\clkdiv.v
...........\clkdiv_assignment_defaults.qdf
...........\clkdiv_nativelink_simulation.rpt
...........\db
...........\..\clkdiv.db_info
...........\..\clkdiv.ipinfo
...........\..\clkdiv.sld_design_entry.sci
...........\..\clkdiv_global_asgn_op.abo
...........\..\logic_util_heursitic.dat
...........\..\prev_cmp_clkdiv.asm.qmsg
...........\..\prev_cmp_clkdiv.eda.qmsg
...........\..\prev_cmp_clkdiv.fit.qmsg
...........\..\prev_cmp_clkdiv.map.qmsg
...........\..\prev_cmp_clkdiv.qmsg
...........\..\prev_cmp_clkdiv.tan.qmsg
...........\incremental_db
...........\..............\README
...........\..............\compiled_partitions
...........\..............\...................\clkdiv.db_info
...........\..............\...................\clkdiv.root_partition.map.kpt
...........\simulation
...........\..........\modelsim
...........\..........\........\clkdiv.sft
...........\..........\........\clkdiv.vo
...........\..........\........\clkdiv.vt
...........\..........\........\clkdiv_modelsim.xrf
...........\..........\........\clkdiv_run_msim_gate_verilog.do
...........\..........\........\clkdiv_run_msim_gate_verilog.do.bak1
...........\..........\........\clkdiv_run_msim_gate_verilog.do.bak2
...........\..........\........\clkdiv_run_msim_rtl_verilog.do
...........\..........\........\clkdiv_run_msim_rtl_verilog.do.bak1
...........\..........\........\clkdiv_run_msim_rtl_verilog.do.bak2
...........\..........\........\clkdiv_run_msim_rtl_verilog.do.bak3
...........\..........\........\clkdiv_run_msim_rtl_verilog.do.bak4
...........\..........\........\clkdiv_run_msim_rtl_verilog.do.bak5
...........\..........\........\clkdiv_run_msim_rtl_verilog.do.bak6
...........\..........\........\clkdiv_run_msim_rtl_verilog.do.bak7
...........\..........\........\clkdiv_v.sdo
...........\..........\........\clkdiv_v.sdo_typ.csd
...........\..........\........\gate_work
...........\..........\........\.........\_info
...........\..........\........\.........\_vmake
...........\..........\........\.........\clkdiv
...........\..........\........\.........\......\_primary.dat
...........\..........\........\.........\......\_primary.dbs
...........\..........\........\.........\......\_primary.vhd
...........\..........\........\.........\......\verilog.prw
...........\..........\........\.........\......\verilog.psm
...........\..........\........\.........\clkdiv_vlg_tst
...........\..........\........\.........\..............\_primary.dat
...........\..........\........\.........\..............\_primary.dbs
...........\..........\........\.........\..............\_primary.vhd
...........\..........\........\.........\..............\verilog.prw
...........\..........\........\.........\..............\verilog.psm
...........\..........\........\modelsim.ini
...........\..........\........\msim_transcript
...........\..........\........\rtl_work
...........\..........\........\........\_info
...........\..........\........\........\_vmake
...........\..........\........\........\clkdiv
...........\..........\........\........\......\_primary.dat
...........\..........\........\........\......\_primary.dbs
...........\..........\........\........\......\_primary.vhd
...........\..........\........\........\......\verilog.prw
...........\..........\........\........\......\verilog.psm
...........\..........\........\........\clkdiv_vlg_tst
...........\..........\........\........\..............\_primary.dat
...........\..........\........\........\..............\_primary.dbs
.........