压缩包 : 5956454veriloghdl_advanced_digital_design_code_ch5.rar 列表
VerilogHDL_advanced_digital_design_code_Ch5\adder_task.v
VerilogHDL_advanced_digital_design_code_Ch5\ADDVB_Models_5.doc
VerilogHDL_advanced_digital_design_code_Ch5\add_4cycle.v
VerilogHDL_advanced_digital_design_code_Ch5\AOI_5_CA0.v
VerilogHDL_advanced_digital_design_code_Ch5\AOI_5_CA1.v
VerilogHDL_advanced_digital_design_code_Ch5\AOI_5_CA2.v
VerilogHDL_advanced_digital_design_code_Ch5\AOI_5_CA3.v
VerilogHDL_advanced_digital_design_code_Ch5\arithmetic_unit.v
VerilogHDL_advanced_digital_design_code_Ch5\asynch_df_behav.v
VerilogHDL_advanced_digital_design_code_Ch5\Auto_LFSR_ALGO.v
VerilogHDL_advanced_digital_design_code_Ch5\Auto_LFSR_Param.v
VerilogHDL_advanced_digital_design_code_Ch5\Auto_LFSR_RTL.v
VerilogHDL_advanced_digital_design_code_Ch5\barrel_shifter.v
VerilogHDL_advanced_digital_design_code_Ch5\comparator.v
VerilogHDL_advanced_digital_design_code_Ch5\compare_2_algo.v
VerilogHDL_advanced_digital_design_code_Ch5\compare_2_CA0.v
VerilogHDL_advanced_digital_design_code_Ch5\compare_2_CA1.txt
VerilogHDL_advanced_digital_design_code_Ch5\compare_2_CA1.v
VerilogHDL_advanced_digital_design_code_Ch5\compare_2_ROM.v
VerilogHDL_advanced_digital_design_code_Ch5\compare_2_RTL.v
VerilogHDL_advanced_digital_design_code_Ch5\compare_32_CA.v
VerilogHDL_advanced_digital_design_code_Ch5\decoder.v
VerilogHDL_advanced_digital_design_code_Ch5\df_behav.v
VerilogHDL_advanced_digital_design_code_Ch5\encoder.v
VerilogHDL_advanced_digital_design_code_Ch5\find_first_one.v
VerilogHDL_advanced_digital_design_code_Ch5\Hex_Keypad_Grayhill_072.v
VerilogHDL_advanced_digital_design_code_Ch5\Latch_CA.v
VerilogHDL_advanced_digital_design_code_Ch5\Latch_Rbar_CA.v
VerilogHDL_advanced_digital_design_code_Ch5\Majority.v
VerilogHDL_advanced_digital_design_code_Ch5\Majority_4b.v
VerilogHDL_advanced_digital_design_code_Ch5\Mux_4_32_CA.v
VerilogHDL_advanced_digital_design_code_Ch5\Mux_4_32_case.v
VerilogHDL_advanced_digital_design_code_Ch5\Mux_4_32_if.v
VerilogHDL_advanced_digital_design_code_Ch5\Par_load_reg4.v
VerilogHDL_advanced_digital_design_code_Ch5\pipe_2stage.v
VerilogHDL_advanced_digital_design_code_Ch5\priority.v
VerilogHDL_advanced_digital_design_code_Ch5\Register_File.v
VerilogHDL_advanced_digital_design_code_Ch5\ring_counter.v
VerilogHDL_advanced_digital_design_code_Ch5\Row_Signal.v
VerilogHDL_advanced_digital_design_code_Ch5\Seven_Seg_Display.v
VerilogHDL_advanced_digital_design_code_Ch5\shiftreg_nb.v
VerilogHDL_advanced_digital_design_code_Ch5\shiftreg_PA.v
VerilogHDL_advanced_digital_design_code_Ch5\shiftreg_PA_rev.v
VerilogHDL_advanced_digital_design_code_Ch5\Shift_reg4.v
VerilogHDL_advanced_digital_design_code_Ch5\shift_reg_PA.v
VerilogHDL_advanced_digital_design_code_Ch5\Synchronizer.v
VerilogHDL_advanced_digital_design_code_Ch5\synchro_2.v
VerilogHDL_advanced_digital_design_code_Ch5\tr_latch.v
VerilogHDL_advanced_digital_design_code_Ch5\t_AOI_5_CA1.v
VerilogHDL_advanced_digital_design_code_Ch5\t_AOI_5_CA2.v
VerilogHDL_advanced_digital_design_code_Ch5\t_Bin_Cnt_Part_RTL.v
VerilogHDL_advanced_digital_design_code_Ch5\t_Hex_Keypad_Grayhill_072.v
VerilogHDL_advanced_digital_design_code_Ch5\t_Latch_CA.v
VerilogHDL_advanced_digital_design_code_Ch5\t_Latch_Rbar_CA.v
VerilogHDL_advanced_digital_design_code_Ch5\Universal_Shift_Reg.v
VerilogHDL_advanced_digital_design_code_Ch5\Universal_Shift_Register.v
VerilogHDL_advanced_digital_design_code_Ch5\up_down_counter.v
VerilogHDL_advanced_digital_design_code_Ch5\Up_Down_Implicit1.v
VerilogHDL_advanced_digital_design_code_Ch5\word_aligner.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\adder_task.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\ADDVB_Models_5.doc
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\add_4cycle.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\AOI_5_CA0.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\AOI_5_CA1.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\AOI_5_CA2.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\AOI_5_CA3.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\arithmetic_unit.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\asynch_df_behav.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\Auto_LFSR_ALGO.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\Auto_LFSR_Param.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\Auto_LFSR_RTL.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\barrel_shifter.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\comparator.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\compare_2_algo.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\compare_2_CA0.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\compare_2_CA1.txt
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\compare_2_CA1.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\compare_2_ROM.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\compare_2_RTL.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\compare_32_CA.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\decoder.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\df_behav.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\encoder.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\find_first_one.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\Hex_Keypad_Grayhill_072.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\Latch_CA.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\Latch_Rbar_CA.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\Majority.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\Majority_4b.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\Mux_4_32_CA.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\Mux_4_32_case.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\Mux_4_32_if.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\Par_load_reg4.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\pipe_2stage.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\priority.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\Register_File.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\ring_counter.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\Row_Signal.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\Seven_Seg_Display.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\shiftreg_nb.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\shiftreg_PA.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\shiftreg_PA_rev.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\Shift_reg4.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\shift_reg_PA.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\Synchronizer.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\synchro_2.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\tr_latch.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\t_AOI_5_CA1.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\t_AOI_5_CA2.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\t_Bin_Cnt_Part_RTL.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\t_Hex_Keypad_Grayhill_072.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\t_Latch_CA.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\t_Latch_Rbar_CA.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\Universal_Shift_Reg.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\Universal_Shift_Register.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\up_down_counter.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\Up_Down_Implicit1.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf\word_aligner.v
VerilogHDL_advanced_digital_design_code_Ch5\_vti_cnf
VerilogHDL_advanced_digital_design_code_Ch5