文件名称:verilog-codes-for-booth2
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由verilog编写的采用booth2编码的16*16乘法器-a 16*16 multiplier with booth2 coding by verilog
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下载文件列表
verilog codes for booth2\boothR4_16bit.v
........................\boothR4_16bit_testbench.v
........................\compressor4_2.v
........................\compressor4_2_tb.v
........................\fulladder.v
........................\halfadder.v
........................\multiplier_16s_testbench.v
........................\multiplier_16s_testbench_shortver.v
........................\multiplier_16s_top.v
........................\sqcsa_part_2bit.v
........................\sqcsa_part_3bit.v
........................\sqcsa_part_4bit.v
........................\sqcsa_part_5bit.v
........................\sqcsa_part_6bit.v
........................\squareroot_csa_32bit.v
........................\squareroot_csa_32bit_testbench.v
........................\wallacetree.v
verilog codes for booth2