文件名称:voter_VHDL
介绍说明－－下载内容均来自于网络，请自行研究使用
这是基于Quartus2开发环境和vhdl语音编译的表决器-voter basic on vhdl and Quartus2
(系统自动生成,下载前可以参看下载内容)
下载文件列表
voter_VHDL
..........\db
..........\..\mux_3nc.tdf
..........\..\mux_umc.tdf
..........\..\prev_cmp_voter_VHDL.asm.qmsg
..........\..\prev_cmp_voter_VHDL.fit.qmsg
..........\..\prev_cmp_voter_VHDL.map.qmsg
..........\..\prev_cmp_voter_VHDL.qmsg
..........\..\prev_cmp_voter_VHDL.sim.qmsg
..........\..\prev_cmp_voter_VHDL.tan.qmsg
..........\..\voter_VHDL.asm.qmsg
..........\..\voter_VHDL.cbx.xml
..........\..\voter_VHDL.cmp.cdb
..........\..\voter_VHDL.cmp.ecobp
..........\..\voter_VHDL.cmp.hdb
..........\..\voter_VHDL.cmp.kpt
..........\..\voter_VHDL.cmp.logdb
..........\..\voter_VHDL.cmp.rdb
..........\..\voter_VHDL.cmp.tdb
..........\..\voter_VHDL.cmp0.ddb
..........\..\voter_VHDL.cmp2.ddb
..........\..\voter_VHDL.cmp_merge.kpt
..........\..\voter_VHDL.db_info
..........\..\voter_VHDL.eco.cdb
..........\..\voter_VHDL.eds_overflow
..........\..\voter_VHDL.fit.qmsg
..........\..\voter_VHDL.fnsim.hdb
..........\..\voter_VHDL.fnsim.qmsg
..........\..\voter_VHDL.hier_info
..........\..\voter_VHDL.hif
..........\..\voter_VHDL.lpc.html
..........\..\voter_VHDL.lpc.rdb
..........\..\voter_VHDL.lpc.txt
..........\..\voter_VHDL.map.cdb
..........\..\voter_VHDL.map.ecobp
..........\..\voter_VHDL.map.hdb
..........\..\voter_VHDL.map.kpt
..........\..\voter_VHDL.map.logdb
..........\..\voter_VHDL.map.qmsg
..........\..\voter_VHDL.pre_map.cdb
..........\..\voter_VHDL.pre_map.hdb
..........\..\voter_VHDL.rpp.qmsg
..........\..\voter_VHDL.rtlv.hdb
..........\..\voter_VHDL.rtlv_sg.cdb
..........\..\voter_VHDL.rtlv_sg_swap.cdb
..........\..\voter_VHDL.sgate.rvd
..........\..\voter_VHDL.sgate_sm.rvd
..........\..\voter_VHDL.sgdiff.cdb
..........\..\voter_VHDL.sgdiff.hdb
..........\..\voter_VHDL.sim.cvwf
..........\..\voter_VHDL.sim.hdb
..........\..\voter_VHDL.sim.qmsg
..........\..\voter_VHDL.sim.rdb
..........\..\voter_VHDL.simfam
..........\..\voter_VHDL.sld_design_entry.sci
..........\..\voter_VHDL.sld_design_entry_dsc.sci
..........\..\voter_VHDL.syn_hier_info
..........\..\voter_VHDL.tan.qmsg
..........\..\voter_VHDL.tis_db_list.ddb
..........\..\voter_VHDL.tmw_info
..........\..\voter_VHDL_global_asgn_op.abo
..........\..\wed.wsf
..........\incremental_db
..........\..............\README
..........\..............\compiled_partitions
..........\..............\...................\voter_VHDL.root_partition.cmp.atm
..........\..............\...................\voter_VHDL.root_partition.cmp.dfp
..........\..............\...................\voter_VHDL.root_partition.cmp.hdbx
..........\..............\...................\voter_VHDL.root_partition.cmp.kpt
..........\..............\...................\voter_VHDL.root_partition.cmp.logdb
..........\..............\...................\voter_VHDL.root_partition.cmp.rcf
..........\..............\...................\voter_VHDL.root_partition.map.atm
..........\..............\...................\voter_VHDL.root_partition.map.dpi
..........\..............\...................\voter_VHDL.root_partition.map.hdbx
..........\..............\...................\voter_VHDL.root_partition.map.kpt
..........\voter_VHDL.asm.rpt
..........\voter_VHDL.done
..........\voter_VHDL.dpf
..........\voter_VHDL.fit.rpt
..........\voter_VHDL.fit.smsg
..........\voter_VHDL.fit.summary
..........\voter_VHDL.flow.rpt
..........\voter_VHDL.map.rpt
..........\voter_VHDL.map.summary
..........\voter_VHDL.pin
..........\voter_VHDL.pof
..........\voter_VHDL.qpf
..........\voter_VHDL.qsf
..........\voter_VHDL.qws
..........\voter_VHDL.sim.rpt
..........\voter_VHDL.sof
..........\voter_VHDL.tan.rpt
..........\voter_VHDL.tan.summary
..........\voter_VHDL.vhd
..........\voter_VHDL.vhd.bak
..........\voter_VHDL.vwf