文件名称:counter10
介绍说明－－下载内容均来自于网络，请自行研究使用
verilog编写的10进制计数器，并且功能仿真正确。软件为quartus II 11.0,和Modelsim-verilog prepared 10 binary counter, and functional simulation is correct. Software quartus II 11.0, and Modelsim
(系统自动生成,下载前可以参看下载内容)
下载文件列表
counter10\counter10.qpf
.........\counter10.qsf
.........\db\counter10.db_info
.........\..\prev_cmp_counter10.qmsg
.........\..\counter10.tis_db_list.ddb
.........\..\counter10.eda.qmsg
.........\..\logic_util_heursitic.dat
.........\..\counter10.rtlv_sg_swap.cdb
.........\..\counter10.cbx.xml
.........\..\counter10.lpc.txt
.........\..\counter10.lpc.html
.........\..\counter10.map.qmsg
.........\..\counter10.smart_action.txt
.........\..\counter10.lpc.rdb
.........\..\counter10.sld_design_entry.sci
.........\..\counter10.pre_map.hdb
.........\..\counter10.pre_map.cdb
.........\..\counter10.map_bb.logdb
.........\..\counter10.sgdiff.cdb
.........\..\counter10.sgdiff.hdb
.........\..\counter10.rtlv_sg.cdb
.........\..\counter10.rtlv.hdb
.........\..\counter10.hif
.........\..\counter10.sld_design_entry_dsc.sci
.........\..\counter10.hier_info
.........\..\counter10.map.cdb
.........\..\counter10.map_bb.cdb
.........\..\counter10.map.hdb
.........\..\counter10.map_bb.hdb
.........\..\counter10.map.logdb
.........\..\counter10.map.bpm
.........\..\counter10.cmp.rdb
.........\..\counter10.cmp.hdb
.........\..\counter10.syn_hier_info
.........\..\counter10.map.kpt
.........\..\counter10.cmp_merge.kpt
.........\counter10.v
.........\release\counter10.map.summary
.........\.......\counter10.done
.........\.......\counter10.map.rpt
.........\.......\counter10.eda.rpt
.........\.......\counter10.flow.rpt
.........\counter10.v.bak
.........\incremental_db\compiled_partitions\counter10.db_info
.........\..............\...................\counter10.root_partition.map.kpt
.........\..............\...................\counter10.root_partition.map.hbdb.hb_info
.........\..............\...................\counter10.root_partition.map.hbdb.sig
.........\..............\...................\counter10.root_partition.map.dpi
.........\..............\...................\counter10.root_partition.map.cdb
.........\..............\...................\counter10.root_partition.map.hdb
.........\..............\...................\counter10.root_partition.map.hbdb.cdb
.........\..............\...................\counter10.root_partition.map.hbdb.hdb
.........\..............\README
.........\work\_info
.........\simulation\modelsim\counter10.vt
.........\..........\........\counter10_run_msim_rtl_verilog.do
.........\..........\........\msim_transcript
.........\..........\........\rtl_work\_info
.........\..........\........\........\_vmake
.........\..........\........\........\counter10\_primary.vhd
.........\..........\........\........\.........\verilog.psm
.........\..........\........\........\.........\verilog.prw
.........\..........\........\........\.........\_primary.dbs
.........\..........\........\........\.........\_primary.dat
.........\..........\........\........\........._vlg_tst\_primary.vhd
.........\..........\........\........\.................\verilog.psm
.........\..........\........\........\.................\verilog.prw
.........\..........\........\........\.................\_primary.dbs
.........\..........\........\........\.................\_primary.dat
.........\..........\........\modelsim.ini
.........\..........\........\vsim.wlf
.........\counter10_nativelink_simulation.rpt
.........\simulation\modelsim\rtl_work\_temp
.........\..........\........\........\counter10
.........\..........\........\........\counter10_vlg_tst
.........\..........\........\rtl_work
.........\incremental_db\compiled_partitions
.........\simulation\modelsim
.........\db
.........\release
.........\incremental_db
.........\work
.........\simulation
counter10