文件名称:JIAFA_4
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加法器，采用流水线技术设计四级加法器，VHDL实验-Adder, four pipelined adder technical design, VHDL test
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下载文件列表
JIAFA_4\db\JIAFA_4.asm.qmsg
.......\..\JIAFA_4.cbx.xml
.......\..\JIAFA_4.cmp.cdb
.......\..\JIAFA_4.cmp.hdb
.......\..\JIAFA_4.cmp.logdb
.......\..\JIAFA_4.cmp.rdb
.......\..\JIAFA_4.cmp.tdb
.......\..\JIAFA_4.cmp0.ddb
.......\..\JIAFA_4.dbp
.......\..\JIAFA_4.db_info
.......\..\JIAFA_4.eco.cdb
.......\..\JIAFA_4.eds_overflow
.......\..\JIAFA_4.fit.qmsg
.......\..\JIAFA_4.hier_info
.......\..\JIAFA_4.hif
.......\..\JIAFA_4.map.cdb
.......\..\JIAFA_4.map.hdb
.......\..\JIAFA_4.map.logdb
.......\..\JIAFA_4.map.qmsg
.......\..\JIAFA_4.pre_map.cdb
.......\..\JIAFA_4.pre_map.hdb
.......\..\JIAFA_4.psp
.......\..\JIAFA_4.pss
.......\..\JIAFA_4.rtlv.hdb
.......\..\JIAFA_4.rtlv_sg.cdb
.......\..\JIAFA_4.rtlv_sg_swap.cdb
.......\..\JIAFA_4.sgdiff.cdb
.......\..\JIAFA_4.sgdiff.hdb
.......\..\JIAFA_4.sim.cvwf
.......\..\JIAFA_4.sim.hdb
.......\..\JIAFA_4.sim.qmsg
.......\..\JIAFA_4.sim.rdb
.......\..\JIAFA_4.sld_design_entry.sci
.......\..\JIAFA_4.sld_design_entry_dsc.sci
.......\..\JIAFA_4.syn_hier_info
.......\..\JIAFA_4.tan.qmsg
.......\..\JIAFA_4.tis_db_list.ddb
.......\..\prev_cmp_JIAFA_4.asm.qmsg
.......\..\prev_cmp_JIAFA_4.fit.qmsg
.......\..\prev_cmp_JIAFA_4.map.qmsg
.......\..\prev_cmp_JIAFA_4.qmsg
.......\..\prev_cmp_JIAFA_4.sim.qmsg
.......\..\prev_cmp_JIAFA_4.tan.qmsg
.......\..\wed.wsf
.......\JIAFA_4.asm.rpt
.......\JIAFA_4.done
.......\JIAFA_4.fit.rpt
.......\JIAFA_4.fit.summary
.......\JIAFA_4.flow.rpt
.......\JIAFA_4.map.rpt
.......\JIAFA_4.map.summary
.......\JIAFA_4.pin
.......\JIAFA_4.qpf
.......\JIAFA_4.qsf
.......\JIAFA_4.qws
.......\JIAFA_4.sim.rpt
.......\JIAFA_4.tan.rpt
.......\JIAFA_4.tan.summary
.......\JIAFA_4.vhd
.......\JIAFA_4.vhd.bak
.......\JIAFA_4.vwf
.......\db
JIAFA_4