文件名称:Enc_With_Punc---2011-11-28-v3.0
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Viterbi 译码打孔和去打孔代码,
,VERILOG 代码，自己写的，包含时钟打孔，-Viterbi Decoder With Puncture and Depuncture， Verilog Code，clock puncture ,
,VERILOG 代码，自己写的，包含时钟打孔，-Viterbi Decoder With Puncture and Depuncture， Verilog Code，clock puncture ,
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Enc_With_Punc - 2011-11-28-v3.0\enc_souc.txt
...............................\my_convolution_7_tb.v
...............................\my_enc_viterbi.v
...............................\enc_my_v7_len7.txt
...............................\Puncture_Top.v
...............................\clock_divid.v
...............................\Puncture_Top.v.bak
...............................\puncture34.v
...............................\puncture_Top_tb.v
...............................\modelsim.ini
...............................\vlog.opt
...............................\puncture_Top_tb.v.bak
...............................\my_enc_viterbi.v.bak
...............................\proj_1.prj
...............................\proj_1.prd
...............................\dec_out.txt
...............................\depuncture34_tb.v
...............................\depuncture.v
...............................\depuncture_top.v
...............................\acsu.v
...............................\bmu.v
...............................\butterfly.v
...............................\d_ff.v
...............................\mux.v
...............................\smu.v
...............................\test_bench_win.v
...............................\depuncture_top.v.bak
...............................\test_viterbi_top
...............................\test_viterbi_top.bak
...............................\test_viterbi_top.v
...............................\test_viterbi_top.xml
...............................\test_viterbi_top_tb.v.bak
...............................\test_viterbi_top.v.bak
...............................\puncture34.v.bak
...............................\depuncture.v.bak
...............................\d_ff.v.bak
...............................\smu.v.bak
...............................\my_dec_out.txt
...............................\vish_stacktrace.vstf
...............................\dpram.v.bak
...............................\rstmem.txt
...............................\top.v.bak
...............................\test_bench_unix.v
...............................\mem.v
...............................\dpram.v
...............................\vsim.wlf
...............................\test_viterbi_top_tb.v
...............................\tcl_stacktrace.txt
...............................\top.v
...............................\work\_info
...............................\....\clock_divid3\_primary.vhd
...............................\....\............\verilog.psm
...............................\....\............\_primary.dat
...............................\....\...........4\_primary.vhd
...............................\....\............\verilog.psm
...............................\....\............\_primary.dat
...............................\....\my_convolution_7_tb\_primary.vhd
...............................\....\...................\verilog.psm
...............................\....\...................\_primary.dat
...............................\....\................\_primary.vhd
...............................\....\................\verilog.psm
...............................\....\................\_primary.dat
...............................\....\puncture_top\_primary.vhd
...............................\....\............\verilog.psm
...............................\....\............\_primary.dat
...............................\....\........34\_primary.vhd
...............................\....\..........\verilog.psm
...............................\....\..........\_primary.dat
...............................\....\.........._tb\_primary.vhd
...............................\....\.............\verilog.psm
...............................\....\.............\_primary.dat
...............................\....\........_@top_tb\_primary.vhd
...............................\....\................\verilog.psm
...............................\....\................\_primary.dat
...............................\....\acsu\_primary.vhd
...............................\....\....\verilog.psm
...............................\....\....\_primary.dat
...............................\....\bmu\_primary.vhd