文件名称:spi_adda

  • 所属分类:
  • Linux驱动
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2013-06-27
  • 文件大小:
  • 2.27mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 王**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

实现FPGA读取AD转换的数据,AD芯片我采用的是ADS7844,采用的是SPI通信方式-achieve the function of read the data from the AD transform chip.the communciation method is SPI.i have tested the code ,and it can work.
(系统自动生成,下载前可以参看下载内容)

下载文件列表





spi_adda\db\logic_util_heursitic.dat

........\..\prev_cmp_spi_adda.asm.qmsg

........\..\prev_cmp_spi_adda.eda.qmsg

........\..\prev_cmp_spi_adda.fit.qmsg

........\..\prev_cmp_spi_adda.map.qmsg

........\..\prev_cmp_spi_adda.qmsg

........\..\prev_cmp_spi_adda.sta.qmsg

........\..\spi_adda.asm.qmsg

........\..\spi_adda.asm.rdb

........\..\spi_adda.asm_labs.ddb

........\..\spi_adda.cbx.xml

........\..\spi_adda.cmp.bpm

........\..\spi_adda.cmp.cbp

........\..\spi_adda.cmp.cdb

........\..\spi_adda.cmp.ecobp

........\..\spi_adda.cmp.hdb

........\..\spi_adda.cmp.kpt

........\..\spi_adda.cmp.logdb

........\..\spi_adda.cmp.rdb

........\..\spi_adda.cmp_merge.kpt

........\..\spi_adda.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd

........\..\spi_adda.cuda_io_sim_cache.31um_ss_1200mv_85c_slow.hsd

........\..\spi_adda.db_info

........\..\spi_adda.eco.cdb

........\..\spi_adda.eda.qmsg

........\..\spi_adda.fit.qmsg

........\..\spi_adda.hier_info

........\..\spi_adda.hif

........\..\spi_adda.lpc.html

........\..\spi_adda.lpc.rdb

........\..\spi_adda.lpc.txt

........\..\spi_adda.map.bpm

........\..\spi_adda.map.cdb

........\..\spi_adda.map.ecobp

........\..\spi_adda.map.hdb

........\..\spi_adda.map.kpt

........\..\spi_adda.map.logdb

........\..\spi_adda.map.qmsg

........\..\spi_adda.map_bb.cdb

........\..\spi_adda.map_bb.hdb

........\..\spi_adda.map_bb.logdb

........\..\spi_adda.pre_map.cdb

........\..\spi_adda.pre_map.hdb

........\..\spi_adda.rpp.qmsg

........\..\spi_adda.rtlv.hdb

........\..\spi_adda.rtlv_sg.cdb

........\..\spi_adda.rtlv_sg_swap.cdb

........\..\spi_adda.sgate.rvd

........\..\spi_adda.sgate_sm.rvd

........\..\spi_adda.sgdiff.cdb

........\..\spi_adda.sgdiff.hdb

........\..\spi_adda.sld_design_entry.sci

........\..\spi_adda.sld_design_entry_dsc.sci

........\..\spi_adda.smart_action.txt

........\..\spi_adda.sta.qmsg

........\..\spi_adda.sta.rdb

........\..\spi_adda.sta_cmp.8_slow_1200mv_85c.tdb

........\..\spi_adda.syn_hier_info

........\..\spi_adda.tiscmp.fastest_slow_1200mv_0c.ddb

........\..\spi_adda.tiscmp.fastest_slow_1200mv_85c.ddb

........\..\spi_adda.tiscmp.fast_1200mv_0c.ddb

........\..\spi_adda.tiscmp.slow_1200mv_0c.ddb

........\..\spi_adda.tiscmp.slow_1200mv_85c.ddb

........\..\spi_adda.tis_db_list.ddb

........\..\spi_adda.tmw_info

........\edge_check.v

........\FIFO_8X8.V

........\incremental_db\compiled_partitions\spi_adda.root_partition.cmp.cdb

........\..............\...................\spi_adda.root_partition.cmp.dfp

........\..............\...................\spi_adda.root_partition.cmp.hdb

........\..............\...................\spi_adda.root_partition.cmp.kpt

........\..............\...................\spi_adda.root_partition.cmp.logdb

........\..............\...................\spi_adda.root_partition.cmp.rcfdb

........\..............\...................\spi_adda.root_partition.cmp.re.rcfdb

........\..............\...................\spi_adda.root_partition.map.cdb

........\..............\...................\spi_adda.root_partition.map.dpi

........\..............\...................\spi_adda.root_partition.map.hdb

........\..............\...................\spi_adda.root_partition.map.kpt

........\..............\README

........\my_uart_tx.v

........\simulation\modelsim\modelsim.ini

........\..........\........\msim_transcript

........\..........\........\rtl_work\spi_adda\verilog.prw

........\..........\........\........\........\verilog.psm

........\..........\........\........\........\_primary.dat

........\..........\........\........\........\_primary.dbs

........\..........\........\........\........\_primary.vhd

........\..........\........\........\........_vlg_tst\verilog.prw

........\..........\........\........\................\verilog.psm

........\..........\........\........\................\_primary.dat

........\..........\........\........\................\_primary.dbs

........\..........\........\........\................\_primary.vhd

........\..........\........\........\_info

........\..........\........\........\_vmake

........\..........\........\spi_adda.sft

........\..........\

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