文件名称:UDP
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这是用Verilog HDL编写的程序
利用UDP方法实现四位加法器-This is written in Verilog HDL programs
Use UDP method four adder
利用UDP方法实现四位加法器-This is written in Verilog HDL programs
Use UDP method four adder
(系统自动生成,下载前可以参看下载内容)
下载文件列表
UDP
...\addr.v
...\addr.v.bak
...\addr4.xml
...\addr4_tb.v
...\addr4_tb.v.bak
...\addr_UDP.cr.mti
...\addr_UDP.mpf
...\transcript
...\vsim.wlf
...\work
...\....\_info
...\....\_temp
...\....\.....\vlog7j416a
...\....\.....\vlogfj0ijs
...\....\.....\vloggcitac
...\....\.....\vloghrn1zt
...\....\.....\vlogigek54
...\....\.....\vlogizq4d6
...\....\.....\vlogjvyzry
...\....\.....\vlogmq8k88
...\....\.....\vlogzv7tgx
...\....\_vmake
...\....\addr1
...\....\.....\_primary.dat
...\....\.....\_primary.dbs
...\....\.....\_primary.vhd
...\....\.....\verilog.asm
...\....\.....\verilog.rw
...\....\addr1_carry
...\....\...........\_primary.dat
...\....\...........\_primary.dbs
...\....\...........\_primary.vhd
...\....\...........\verilog.asm
...\....\...........\verilog.rw
...\....\addr1_sum
...\....\.........\_primary.dat
...\....\.........\_primary.dbs
...\....\.........\_primary.vhd
...\....\.........\verilog.asm
...\....\.........\verilog.rw
...\....\addr4
...\....\.....\_primary.dat
...\....\.....\_primary.dbs
...\....\.....\_primary.vhd
...\....\.....\verilog.asm
...\....\.....\verilog.rw
...\....\addr4_tb
...\....\........\_primary.dat
...\....\........\_primary.dbs
...\....\........\_primary.vhd
...\....\........\verilog.asm
...\....\........\verilog.rw