用Verilog HDL设计一个4bit变模计数器和一个5bit二进制加法器。在4bit输入cipher的控制下，实现同步模5、模8、模10、模12及用任务调用语句实现的5bit二进制加法器，计数器具有同步清零和暂停计数的功能。主频为50MHz，要求显示频率为1Hz。-A 4-bit variable modulus counter and a 5bit of binary adder using Verilog HDL design. 4bit input under the control of the cipher achieve synchronous mode 5, the die 8, a mold 10, the mold 12 and the task calls statement 5bit binary adder, a counter with synchronous clear and pause count function. Clocked at 50MHz, display frequency to 1 Hz.