文件名称:clock1
介绍说明－－下载内容均来自于网络，请自行研究使用
该代码实现的是使用VHDL语言编程实现的FPGA上的时钟分频。通过修改代码中的参数改变FPGA的输出时钟频率。-The code implements the VHDL language programming on the FPGA clock divider. Changed by modifying the parameters in the code of the output clock frequency of the FPGA.
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下载文件列表
clock1
......\Project.dhp
......\__ISE_repository_clock1.ise_.lock
......\__projnav.log
......\_impact.cmd
......\_impact.log
......\_ngo
......\....\netlist.lst
......\_pace.ucf
......\_xmsgs
......\......\bitgen.xmsgs
......\......\map.xmsgs
......\......\ngdbuild.xmsgs
......\......\par.xmsgs
......\......\trce.xmsgs
......\......\xst.xmsgs
......\automake.log
......\bitgen.ut
......\clock1.bgn
......\clock1.bit
......\clock1.bld
......\clock1.cmd_log
......\clock1.dhp
......\clock1.drc
......\clock1.ise
......\clock1.ise.old
......\clock1.ise_ISE_Backup
......\clock1.isim_stx_prj
......\clock1.isim_stx_sim
......\clock1.lfp
......\clock1.lso
......\clock1.mrp
......\clock1.msd
......\clock1.msk
......\clock1.ncd
......\clock1.ngc
......\clock1.ngd
......\clock1.ngm
......\clock1.ngr
......\clock1.ntrc_log
......\clock1.pad
......\clock1.par
......\clock1.par_nlf
......\clock1.pcf
......\clock1.prj
......\clock1.rbb
......\clock1.rbd
......\clock1.restore
......\clock1.stx
......\clock1.syr
......\clock1.twr
......\clock1.twx
......\clock1.ucf
......\clock1.unroutes
......\clock1.ut
......\clock1.vhd
......\clock1.xpi
......\clock1.xst
......\clock1_guide.ncd
......\clock1_ise9migration.zip
......\clock1_last_par.ncd
......\clock1_map.map
......\clock1_map.mrp
......\clock1_map.ncd
......\clock1_map.ngm
......\clock1_pad.csv
......\clock1_pad.txt
......\clock1_prev_built.ngd
......\clock1_stx.prj
......\clock1_summary.html
......\clock1_summary.xml
......\clock1_timesim.nlf
......\clock1_timesim.sdf
......\clock1_timesim.vhd
......\clock1_usage.xml
......\clock1_vhdl.prj
......\device_usage_statistics.html
......\disp.vhd
......\drive.vhd
......\isim.cmd
......\isim.hdlsourcefiles
......\isim.tmp_save
......\.............\_1
......\isimwavedata.xwv
......\math.lso
......\math.prj
......\math.stx
......\math_vhdl.prj
......\pepExtractor.prj
......\prjname.lso
......\simprim.auxlib
......\..............\hdllib.ref
......\..............\vcomponents
......\..............\...........\mingw
......\..............\...........\.....\vcomponents.obj
......\..............\...........\vcomponents.h
......\..............\vpackage
......\..............\........\mingw
......\..............\........\.....\vpackage.obj
......\..............\........\vpackage.h