文件名称:vga_lcd
介绍说明－－下载内容均来自于网络，请自行研究使用
这个是VGA的核是NOIS开发时使用的IP CORES 在FPGA的开发中使用的比较多
(系统自动生成,下载前可以参看下载内容)
下载文件列表
压缩包 : 107215771vga_lcd.rar 列表 vga_lcd\bench\verilog\sync_check.v vga_lcd\bench\verilog\tests.v vga_lcd\bench\verilog\test_bench_top.v vga_lcd\bench\verilog\wb_b3_check.v vga_lcd\bench\verilog\wb_mast_model.v vga_lcd\bench\verilog\wb_model_defines.v vga_lcd\bench\verilog\wb_slv_model.v vga_lcd\doc\src\vga_core_enh.doc vga_lcd\doc\vga_core.pdf vga_lcd\rtl\verilog\generic_dpram.v vga_lcd\rtl\verilog\generic_spram.v vga_lcd\rtl\verilog\timescale.v vga_lcd\rtl\verilog\vga_clkgen.v vga_lcd\rtl\verilog\vga_colproc.v vga_lcd\rtl\verilog\vga_csm_pb.v vga_lcd\rtl\verilog\vga_curproc.v vga_lcd\rtl\verilog\vga_cur_cregs.v vga_lcd\rtl\verilog\vga_defines.v vga_lcd\rtl\verilog\vga_enh_top.v vga_lcd\rtl\verilog\vga_fifo.v vga_lcd\rtl\verilog\vga_fifo_dc.v vga_lcd\rtl\verilog\vga_pgen.v vga_lcd\rtl\verilog\vga_tgen.v vga_lcd\rtl\verilog\vga_vtim.v vga_lcd\rtl\verilog\vga_wb_master.v vga_lcd\rtl\verilog\vga_wb_slave.v vga_lcd\rtl\vhdl\colproc.vhd vga_lcd\rtl\vhdl\counter.vhd vga_lcd\rtl\vhdl\csm_pb.vhd vga_lcd\rtl\vhdl\dpm.vhd vga_lcd\rtl\vhdl\fifo.vhd vga_lcd\rtl\vhdl\fifo_dc.vhd vga_lcd\rtl\vhdl\pgen.vhd vga_lcd\rtl\vhdl\tgen.vhd vga_lcd\rtl\vhdl\vga.vhd vga_lcd\rtl\vhdl\vga_and_clut.vhd vga_lcd\rtl\vhdl\vga_and_clut_tstbench.vhd vga_lcd\rtl\vhdl\vtim.vhd vga_lcd\rtl\vhdl\wb_master.vhd vga_lcd\rtl\vhdl\wb_slave.vhd vga_lcd\sim\rtl_sim\bin\Makefile vga_lcd\software\include\oc_vga_lcd.h vga_lcd\syn\bin\comp.dc vga_lcd\syn\bin\design_spec.dc vga_lcd\syn\bin\lib_spec.dc vga_lcd\syn\bin\read.dc vga_lcd\sim\rtl_sim\bin vga_lcd\sim\rtl_sim\run vga_lcd\bench\verilog vga_lcd\doc\src vga_lcd\rtl\verilog vga_lcd\rtl\vhdl vga_lcd\sim\rtl_sim vga_lcd\software\drivers vga_lcd\software\include vga_lcd\syn\bin vga_lcd\syn\log vga_lcd\syn\out vga_lcd\syn\run vga_lcd\bench vga_lcd\doc vga_lcd\rtl vga_lcd\sim vga_lcd\software vga_lcd\syn vga_lcd