文件名称:H.264_verilog
介绍说明－－下载内容均来自于网络，请自行研究使用
这时H.264编码器的verilog源码，有需要的朋友下载-At this time download the the H.264 encoder Verilog source code, a friend in need
(系统自动生成,下载前可以参看下载内容)
下载文件列表
H.264_verilog\Beha_BitStream_ram.v
.............\BitStream_buffer.v
.............\BitStream_controller.v
.............\bitstream_gclk_gen.v
.............\BitStream_parser_FSM_gating.v
.............\bs_decoding.v
.............\cavlc_consumed_bits_decoding.v
.............\cavlc_decoder.v
.............\CodedBlockPattern_decoding.v
.............\dependent_variable_decoding.v
.............\DF_mem_ctrl.v
.............\DF_pipeline.v
.............\DF_reg_ctrl.v
.............\DF_top.v
.............\end_of_blk_decoding.v
.............\exp_golomb_decoding.v
.............\ext_frame_RAM0_wrapper.v
.............\ext_frame_RAM1_wrapper.v
.............\ext_RAM_ctrl.v
.............\H.264.cr.mti
.............\H.264.mpf
.............\heading_one_detector.v
.............\hybrid_pipeline_ctrl.v
.............\Inter_mv_decoding.v
.............\Inter_pred_CPE.v
.............\Inter_pred_LPE.v
.............\Inter_pred_pipeline.v
.............\Inter_pred_reg_ctrl.v
.............\Inter_pred_sliding_window.v
.............\Inter_pred_top.v
.............\Intra4x4_PredMode_decoding.v
.............\Intra_pred_PE.v
.............\Intra_pred_pipeline.v
.............\Intra_pred_reg_ctrl.v
.............\Intra_pred_top.v
.............\IQIT.v
.............\level_decoding.v
.............\nC_decoding.v
.............\nova.v
.............\nova_defines.v
.............\nova_tb.v
.............\NumCoeffTrailingOnes_decoding.v
.............\pc_decoding.v
.............\QP_decoding.v
.............\ram_async_1r_sync_1w.v
.............\ram_sync_1r_sync_1w.v
.............\reconstruction.v
.............\rec_DF_RAM0_96x32.v
.............\rec_DF_RAM0_wrapper.v
.............\rec_DF_RAM1_96x32.v
.............\rec_DF_RAM1_wrapper.v
.............\rec_DF_RAM_ctrl.v
.............\rec_gclk_gen.v
.............\..v_1\Intra_pred_PE.areasrr
.............\.....\Intra_pred_PE.edn
.............\.....\Intra_pred_PE.fse
.............\.....\Intra_pred_PE.sdf
.............\.....\Intra_pred_PE.srd
.............\.....\Intra_pred_PE.srm
.............\.....\Intra_pred_PE.srr
.............\.....\Intra_pred_PE.srs
.............\.....\Intra_pred_PE.tlg
.............\.....\Intra_pred_PE_sdc.sdc
.............\.....\syntmp\Intra_pred_PE.msg
.............\.....\......\Intra_pred_PE.plg
.............\run_decoding.v
.............\sum.v
.............\syntax_decoding.v
.............\timescale.v
.............\total_zeros_decoding.v
.............\vsim.wlf
.............\work\@inter_pred_reg_ctrl\_primary.dat
.............\....\....................\_primary.vhd
.............\....\....ra4x4_@pred@mode_decoding\verilog.asm
.............\....\.............................\_primary.dat
.............\....\.............................\_primary.vhd
.............\....\......_pred_@p@e\verilog.asm
.............\....\................\_primary.dat
.............\....\................\_primary.vhd
.............\....\............pipeline\_primary.dat
.............\....\....................\_primary.vhd
.............\....\............reg_ctrl\_primary.dat
.............\....\....................\_primary.vhd
.............\....\............top\verilog.asm
.............\....\...............\_primary.dat
.............\....\...............\_primary.vhd
.............\....\.p@e\verilog.asm
.............\....\....\_primary.dat
.............\....\....\_primary.vhd
.............\....\main_seed_precomputation\_primary.dat
.............\....\........................\_primary.vhd
.............\....\plane_@h@v_precomputation\_primary.dat
.............\....\.........................\_primary.vhd
.............\....\......a_precomputation\_primary.dat
.............\....\......................\_primary.vhd
.............\....\......bc_precomputation\_primary.dat
.............\....\.......................\_primary.vhd
.............\....\ram_sync_1r_sync_1w\_primary.dat
.............\....\...................\_primary.vhd
.............\....\_info