文件名称:VeriRISC_CPU_Verilog
介绍说明－－下载内容均来自于网络，请自行研究使用
Verilog硬件描述语言实现VeriRISC CPU。模块包含：8位寄存器，5位计数器，32*8 RAM，8位ALU，MUX，顺序控制器，时钟生成器。包含TB。-This code is to model a VeriRISC CPU. It incorporates several modules: 8-bit register, 5-bit counter, 32 by 8 RAM, 8-bit ALU, scalable MUX, sequence controller, and clock generator. Testbench is included.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
aasd.v
alu.v
clk_gen.v
control.v
counter.v
cpu.v
initmem.dat
mem32by8.v
register.v
scale_mux.v
tb_cpu.v