文件名称:_12_DA[TLC5615]_1

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2013-04-11
  • 文件大小:
  • 2.85mb
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  • 0次
  • 提 供 者:
  • 江*
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通过DA输出正弦波,频率1KHz

ad采用的是TLC5615

输出的正弦波与理想波形基本一样-DA output sine wave frequency 1KHz

The ad is TLC5615

The sine wave output with the ideal waveform is basically the same
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下载文件列表





_12_DA[TLC5615]_1\Modelsim\DAC.cr.mti

.................\........\DAC.mpf

.................\........\sim.do

.................\........\vsim.wlf

.................\........\work\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\verilog.asm

.................\........\....\..........................................\_primary.dat

.................\........\....\..........................................\_primary.vhd

.................\........\....\..............m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n\_primary.dat

.................\........\....\...............................................\_primary.vhd

.................\........\....\...................m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n\verilog.asm

.................\........\....\...........................................................\_primary.dat

.................\........\....\...........................................................\_primary.vhd

.................\........\....\.d@a@c_5615_@c@t@l\verilog.asm

.................\........\....\..................\_primary.dat

.................\........\....\..................\_primary.vhd

.................\........\....\.................._tb\_primary.dat

.................\........\....\.....................\_primary.vhd

.................\........\....\.......@s@i@n@e_1@k\verilog.asm

.................\........\....\...................\_primary.dat

.................\........\....\...................\_primary.vhd

.................\........\....\..................._tb\verilog.asm

.................\........\....\......................\_primary.dat

.................\........\....\......................\_primary.vhd

.................\........\....\.m@f_cycloneiii_pll\_primary.dat

.................\........\....\...................\_primary.vhd

.................\........\....\.....pll_reg\_primary.dat

.................\........\....\............\_primary.vhd

.................\........\....\.....stratixiii_pll\_primary.dat

.................\........\....\...................\_primary.vhd

.................\........\....\.............._pll\_primary.dat

.................\........\....\..................\_primary.vhd

.................\........\....\............_pll\_primary.dat

.................\........\....\................\_primary.vhd

.................\........\....\.r@o@m\verilog.asm

.................\........\....\......\_primary.dat

.................\........\....\......\_primary.vhd

.................\........\....\alt3pram\_primary.dat

.................\........\....\........\_primary.vhd

.................\........\....\...accumulate\_primary.dat

.................\........\....\.............\_primary.vhd

.................\........\....\...cam\_primary.dat

.................\........\....\......\_primary.vhd

.................\........\....\....lklock\_primary.dat

.................\........\....\..........\_primary.vhd

.................\........\....\...ddio_bidir\_primary.dat

.................\........\....\.............\_primary.vhd

.................\........\....\........in\_primary.dat

.................\........\....\..........\_primary.vhd

.................\........\....\........out\_primary.dat

.................\........\....\...........\_primary.vhd

.................\........\....\....pram\_primary.dat

.................\........\....\........\_primary.vhd

.................\........\....\....q_dqs\_primary.dat

.................\........\....\.........\_primary.vhd

.................\........\....\...era_std_synchronizer\_primary.dat

.................\........\....\.......................\_primary.vhd

.................\........\....\......................._bundle\_primary.dat

.................\........\....\..............................\_primary.vhd

.................\........\....\...fp_mult\_primary.dat

.................\........\....\..........\_primary.vhd

.................\........\....\...lvds_rx\_primary.dat

.................\........\....\..........\_primary.vhd

.................\........\....\........tx\_primary.dat

.................\........\....\..........\_primary.vhd

.................\........\....\...mult_accum\_prim

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