文件名称:cache
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基于MIPS思维方式,verilog语言,简单的cache 控制器设计,状态机共分4个状态,同时内含多样测试文件-MIPS way of thinking, verilog language, simple cache controller state machine is divided into four states, at the same time contains diverse test file
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下载文件列表
cache\sim\cache1.cr.mti
.....\...\cache1.mpf
.....\...\vsim.wlf
.....\...\work\@_opt\vopt0c90yx
.....\...\....\.....\vopt0cax3x
.....\...\....\.....\vopt70rs1i
.....\...\....\.....\vopt7jqqnh
.....\...\....\.....\voptas8hax
.....\...\....\.....\voptb3dknh
.....\...\....\.....\voptbgdn1i
.....\...\....\.....\vopte9yeax
.....\...\....\.....\voptei4g1h
.....\...\....\.....\voptf03j1i
.....\...\....\.....\vopti2td1h
.....\...\....\.....\voptiftgch
.....\...\....\.....\voptisjaax
.....\...\....\.....\voptm097dx
.....\...\....\.....\voptm9fa4h
.....\...\....\.....\voptnzfcch
.....\...\....\.....\vopts659fh
.....\...\....\.....\vopts7y4gx
.....\...\....\.....\voptsxy7rx
.....\...\....\.....\voptwej1jx
.....\...\....\.....\voptx4k3vx
.....\...\....\.....\voptx4t6mh
.....\...\....\.....\_deps
.....\...\....\cache_controller\_primary.dat
.....\...\....\................\_primary.dbs
.....\...\....\................\_primary.vhd
.....\...\....\................_00_tb\_primary.dat
.....\...\....\......................\_primary.dbs
.....\...\....\......................\_primary.vhd
.....\...\....\.................hit12_tb\_primary.dat
.....\...\....\.........................\_primary.dbs
.....\...\....\.........................\_primary.vhd
.....\...\....\.................miss1_tb\_primary.dat
.....\...\....\.........................\_primary.dbs
.....\...\....\.........................\_primary.vhd
.....\...\....\.....................2_tb\_primary.dat
.....\...\....\.........................\_primary.dbs
.....\...\....\.........................\_primary.vhd
.....\...\....\.................tb\_primary.dat
.....\...\....\...................\_primary.dbs
.....\...\....\...................\_primary.vhd
.....\...\....\.ounter_n\_primary.dat
.....\...\....\.........\_primary.dbs
.....\...\....\.........\_primary.vhd
.....\...\....\.........2\_primary.dat
.....\...\....\..........\_primary.dbs
.....\...\....\..........\_primary.vhd
.....\...\....\........._tb_v\_primary.dat
.....\...\....\..............\_primary.dbs
.....\...\....\..............\_primary.vhd
.....\...\....\_info
.....\...\....\.temp\vlogz02b08
.....\...\....\.....\vlogzn3be7
.....\...\....\_vmake
.....\.rc\cache_controller.v
.....\...\cache_controller_00000000.v.bak
.....\...\cache_controller_00_tb.v
.....\...\cache_controller_00_tb.v.bak
.....\...\cache_controller_hit12_tb.v
.....\...\cache_controller_hit12_tb.v.bak
.....\...\cache_controller_hit1_tb.v.bak
.....\...\cache_controller_miss1_tb.v
.....\...\cache_controller_miss1_tb.v.bak
.....\...\cache_controller_miss2_tb.v
.....\...\cache_controller_miss2_tb.v.bak
.....\...\cache_controller_tb.v
.....\...\cache_controller_tb.v.bak
.....\...\cache_controller_tb_2.v
.....\...\counter_n.v.bak
.....\...\counter_n2.v
.....\...\counter_n2.v.bak
.....\...\counter_n_tb.v
.....\...\counter_n_tb.v.bak
.....\.im\work\@_opt
.....\...\....\cache_controller
.....\...\....\cache_controller_00_tb
.....\...\....\cache_controller_hit12_tb
.....\...\....\cache_controller_miss1_tb
.....\...\....\cache_controller_miss2_tb
.....\...\....\cache_controller_tb
.....\...\....\counter_n
.....\...\....\counter_n2
.....\...\....\counter_n_tb_v
.....\...\....\_temp
.....\...\work
.....\sim
.....\src
cache