文件名称:fifoVerilog
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设计一个异步FIFO,完成数据平滑功能,FIFO的深度为256,宽度为8位,实时给出读空和溢出指示,写时钟为带间隔的100MHz,读时钟为5MHz,代码为了便于读阅,存放在word文档,可直接拷贝到quartus或者ise编译平台下使用-Design an asynchronous FIFO, complete data smoothing function, the depth of the FIFO 256, and the width is 8 bits, real read empty and overflow indication is given, the write clock for the 100MHz band interval, the read clock is 5MHz, the code in order to facilitate the read access, storage In the word document, can be directly copied to the quartus, or ise compile platform use
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fifoVerilog.doc