文件名称:LAB-16
介绍说明－－下载内容均来自于网络，请自行研究使用
用FPGA实现的性线反馈移位寄存器（LFSR）设计。整个工程在quartusII环境下，用verilog编程。-FPGA implementation of the line feedback shift register (LFSR) design. The whole project in verilog programming the quartusII environment.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
LAB 16\clk_div.bsf
......\clk_div.v
......\db\design.asm.qmsg
......\..\design.asm_labs.ddb
......\..\design.cbx.xml
......\..\design.cmp.cdb
......\..\design.cmp.hdb
......\..\design.cmp.logdb
......\..\design.cmp.rdb
......\..\design.cmp.tdb
......\..\design.cmp0.ddb
......\..\design.cmp2.ddb
......\..\design.db_info
......\..\design.eco.cdb
......\..\design.fit.qmsg
......\..\design.hier_info
......\..\design.hif
......\..\design.map.cdb
......\..\design.map.hdb
......\..\design.map.logdb
......\..\design.map.qmsg
......\..\design.pre_map.cdb
......\..\design.pre_map.hdb
......\..\design.rtlv.hdb
......\..\design.rtlv_sg.cdb
......\..\design.rtlv_sg_swap.cdb
......\..\design.sgdiff.cdb
......\..\design.sgdiff.hdb
......\..\design.signalprobe.cdb
......\..\design.sim.vwf
......\..\design.sld_design_entry.sci
......\..\design.sld_design_entry_dsc.sci
......\..\design.syn_hier_info
......\..\design.tan.qmsg
......\..\design.tis_db_list.ddb
......\..\design.tmw_info
......\..\wed.zsf
......\design.asm.rpt
......\design.bdf
......\design.cdf
......\design.done
......\design.dpf
......\design.fit.rpt
......\design.fit.smsg
......\design.fit.summary
......\design.flow.rpt
......\design.map.rpt
......\design.map.summary
......\design.pin
......\design.pof
......\design.qpf
......\design.qsf
......\design.qws
......\design.sim.rpt
......\design.sim.vwf
......\design.sof
......\design.tan.rpt
......\design.tan.summary
......\design.vwf
......\design_assignment_defaults.qdf
......\LFSR8_8E.bsf
......\LFSR8_8E.v
......\db
LAB 16