文件名称:ethmac10_100M
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以太网IP Core 它实现10/100 Mbps的MAC控制器功能。它是在IEEE802.3和802.3u 标准下设计实现的。-The Ethernet IP Core is a 10/100 Media Access Controller (MAC). It consists of a synthesizable Verilog RTL core that provides all features necessary to implement the Layer 2 protocol of
the Ethernet standard. It is designed to run
according to the IEEE 802.3 and 802.3u
specifications that define the 10 Mbps and 100 Mbps Ethernet standards, respectively.
the Ethernet standard. It is designed to run
according to the IEEE 802.3 and 802.3u
specifications that define the 10 Mbps and 100 Mbps Ethernet standards, respectively.
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下载文件列表
ethmac\branches\unneback\bench\verilog\eth_host.v
......\........\........\.....\.......\eth_memory.v
......\........\........\.....\.......\eth_phy.v
......\........\........\.....\.......\eth_phy_defines.v
......\........\........\.....\.......\tb_cop.v
......\........\........\.....\.......\tb_ethernet.v
......\........\........\.....\.......\tb_ethernet_with_cop.v
......\........\........\.....\.......\tb_eth_defines.v
......\........\........\.....\.......\tb_eth_top.v
......\........\........\.....\.......\wb_bus_mon.v
......\........\........\.....\.......\wb_master32.v
......\........\........\.....\.......\wb_master_behavioral.v
......\........\........\.....\.......\wb_model_defines.v
......\........\........\.....\.......\wb_slave_behavioral.v
......\........\........\doc\ethernet_datasheet_OC_head.pdf
......\........\........\...\ethernet_product_brief_OC_head.pdf
......\........\........\...\eth_design_document.pdf
......\........\........\...\eth_speci.pdf
......\........\........\...\src\ethernet_datasheet_OC_head.doc
......\........\........\...\...\ethernet_product_brief_OC_head.doc
......\........\........\...\...\eth_design_document.doc
......\........\........\...\...\eth_speci.doc
......\........\........\Makefile
......\........\........\README.txt
......\........\........\rtl\verilog\BUGS
......\........\........\...\.......\eth_clockgen.v
......\........\........\...\.......\eth_cop.v
......\........\........\...\.......\eth_crc.v
......\........\........\...\.......\eth_defines.v
......\........\........\...\.......\eth_fifo.v
......\........\........\...\.......\eth_maccontrol.v
......\........\........\...\.......\eth_macstatus.v
......\........\........\...\.......\eth_miim.v
......\........\........\...\.......\eth_outputcontrol.v
......\........\........\...\.......\eth_random.v
......\........\........\...\.......\eth_receivecontrol.v
......\........\........\...\.......\eth_register.v
......\........\........\...\.......\eth_registers.v
......\........\........\...\.......\eth_rxaddrcheck.v
......\........\........\...\.......\eth_rxcounters.v
......\........\........\...\.......\eth_rxethmac.v
......\........\........\...\.......\eth_rxstatem.v
......\........\........\...\.......\eth_shiftreg.v
......\........\........\...\.......\eth_spram_256x32.v
......\........\........\...\.......\eth_top.v
......\........\........\...\.......\eth_transmitcontrol.v
......\........\........\...\.......\eth_txcounters.v
......\........\........\...\.......\eth_txethmac.v
......\........\........\...\.......\eth_txstatem.v
......\........\........\...\.......\eth_wishbone.v
......\........\........\...\.......\Makefile
......\........\........\...\.......\timescale.v
......\........\........\...\.......\TODO
......\........\........\...\.......\xilinx_dist_ram_16x32.v
......\........\........\scripts\icarus.scr
......\........\........\.......\Makefile
......\........\........\.im\rtl_sim\bin\artisan_file_list.lst
......\........\........\...\.......\...\cds.lib
......\........\........\...\.......\...\hdl.var
......\........\........\...\.......\...\INCA_libs\worklib\dir_keeper
......\........\........\...\.......\...\ncelab.args
......\........\........\...\.......\...\ncelab_xilinx.args
......\........\........\...\.......\...\ncsim.rc
......\........\........\...\.......\...\ncsim_waves.rc
......\........\........\...\.......\...\rtl_file_list.lst
......\........\........\...\.......\...\run_sim
......\........\........\...\.......\...\sim_file_list.lst
......\........\........\...\.......\...\xilinx_file_list.lst
......\........\........\...\.......\log\dir_keeper
......\........\........\...\.......\modelsim_sim\bin\do.do
......\........\........\...\.......\............\...\ethernet.mpf
......\........\........\...\.......\............\...\eth_wave.do
......\........\........\...\.......\............\...\vlog.opt
......\........\........\...\.......\............\...\work\dir.keeper
......\........\........\...\.......\............\...\....\_info
......\........\........\...\.......\.........