文件名称:lab4_files
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关于VHDL 状态机的讲解分析 及源代码-Explain the analysis and source code on the state machine in VHDL
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下载文件列表
example1_aldec
..............\code_conv_2processes.vhd
..............\README.txt
..............\shift_register.vhd
..............\testbench_top_level.vhd
..............\top_level.vhd
example1_ise
............\ck_divider.vhd
............\code_conv_2processes.vhd
............\shift_register.vhd
............\top_level.ucf
............\top_level.vhd
example2
........\implementation_A
........\................\fsmd.pdf
........\................\top_level_bit_diff_impl_A.vhd
........\implementation_B
........\................\add.vhd
........\................\comp.vhd
........\................\datapath.pdf
........\................\datapath.vhd
........\................\fsm.vhd
........\................\fsmd.pdf
........\................\mux2x1.vhd
........\................\reg.vhd
........\................\sub.vhd
........\................\top_level.vhd
........\................\top_level_bit_diff_impl_B.vhd
........\README.txt
lab4_FSM.pdf