文件名称:verilog-typical
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作为学习的经典常用例子，可以作为初学者的必备学习例子。-as the typical code for the new verilog learners
(系统自动生成,下载前可以参看下载内容)
下载文件列表
verilog typical\ADC_16bit.v
...............\adder_8bit.v
...............\adder_8bit_2.v
...............\ALL.V
...............\binarytogray.v
...............\cla_8bits.v
...............\COMPARE.V
...............\dds.v.txt
...............\DECODER1.V
...............\decoder3x8.v
...............\div16.v.txt
...............\encoder8x3.v
...............\encoder8x3_2.v
...............\FIFO.V
...............\fifo.v.txt
...............\fifo_16x16.v
...............\FIFO_2.V
...............\framer.v.txt
...............\frequency5x2.v
...............\full_adder_1.v
...............\full_adder_2.v
...............\gencrc.v.txt
...............\half_adder_1.v
...............\half_adder_2.v
...............\half_adder_3.v
...............\lead_8bits_adder.v
...............\lead_8bits_adder2.v
...............\MUL16.V
...............\mult16.v.txt
...............\multi_select_1.v
...............\mult_piped_8x8.v
...............\mult_select.v
...............\MUX8X8.V
...............\myrand.c.txt
...............\nco.v.txt
...............\onehot.v.txt
...............\pic.v.txt
...............\PLI.TAR
...............\RISC8.ZIP
...............\sequence_dectect.v
...............\SHIFTER.V
...............\string.v.txt
...............\SYNTHPIC.ZIP
...............\TEST.V
...............\testing.v.txt
...............\test_cla_8bits.v
...............\wpulse.v.txt
verilog typical