文件名称:SinPout
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FPGA设计中涉及到的速度与面积互换技巧，本工程的代码用Verilog编写，实现功能串行输入并行输出-It comes to speed and area interchangeable FPGA design skills, the project code written in Verilog function serial input parallel output
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下载文件列表
SinPout\db\logic_util_heursitic.dat
.......\..\prev_cmp_sp.qmsg
.......\..\sp.map_bb.logdb
.......\..\sp_top.amm.cdb
.......\..\sp_top.asm.qmsg
.......\..\sp_top.asm.rdb
.......\..\sp_top.cbx.xml
.......\..\sp_top.cmp.bpm
.......\..\sp_top.cmp.cbp
.......\..\sp_top.cmp.cdb
.......\..\sp_top.cmp.hdb
.......\..\sp_top.cmp.kpt
.......\..\sp_top.cmp.logdb
.......\..\sp_top.cmp.rdb
.......\..\sp_top.cmp.tdb
.......\..\sp_top.cmp0.ddb
.......\..\sp_top.cmp_merge.kpt
.......\..\sp_top.db_info
.......\..\sp_top.eda.qmsg
.......\..\sp_top.fit.qmsg
.......\..\sp_top.hier_info
.......\..\sp_top.hif
.......\..\sp_top.idb.cdb
.......\..\sp_top.lpc.html
.......\..\sp_top.lpc.rdb
.......\..\sp_top.lpc.txt
.......\..\sp_top.map.bpm
.......\..\sp_top.map.cbp
.......\..\sp_top.map.cdb
.......\..\sp_top.map.hdb
.......\..\sp_top.map.kpt
.......\..\sp_top.map.qmsg
.......\..\sp_top.map_bb.cdb
.......\..\sp_top.map_bb.hdb
.......\..\sp_top.pre_map.cdb
.......\..\sp_top.pre_map.hdb
.......\..\sp_top.rtlv.hdb
.......\..\sp_top.rtlv_sg.cdb
.......\..\sp_top.rtlv_sg_swap.cdb
.......\..\sp_top.sgdiff.cdb
.......\..\sp_top.sgdiff.hdb
.......\..\sp_top.sld_design_entry.sci
.......\..\sp_top.sld_design_entry_dsc.sci
.......\..\sp_top.smart_action.txt
.......\..\sp_top.syn_hier_info
.......\..\sp_top.tan.qmsg
.......\..\sp_top.tis_db_list.ddb
.......\..\sp_top.tmw_info
.......\incremental_db\compiled_partitions\sp_top.db_info
.......\..............\...................\sp_top.root_partition.cmp.cdb
.......\..............\...................\sp_top.root_partition.cmp.dfp
.......\..............\...................\sp_top.root_partition.cmp.hdb
.......\..............\...................\sp_top.root_partition.cmp.kpt
.......\..............\...................\sp_top.root_partition.cmp.logdb
.......\..............\...................\sp_top.root_partition.cmp.rcfdb
.......\..............\...................\sp_top.root_partition.cmp.re.rcfdb
.......\..............\...................\sp_top.root_partition.map.cdb
.......\..............\...................\sp_top.root_partition.map.dpi
.......\..............\...................\sp_top.root_partition.map.hdb
.......\..............\...................\sp_top.root_partition.map.kpt
.......\..............\README
.......\parallel_out.v
.......\parallel_out.v.bak
.......\series_in.v
.......\series_in.v.bak
.......\.imulation\modelsim\modelsim.ini
.......\..........\........\msim_transcript
.......\..........\........\rtl_work\parallel_out\verilog.prw
.......\..........\........\........\............\verilog.psm
.......\..........\........\........\............\_primary.dat
.......\..........\........\........\............\_primary.dbs
.......\..........\........\........\............\_primary.vhd
.......\..........\........\........\series_in\verilog.prw
.......\..........\........\........\.........\verilog.psm
.......\..........\........\........\.........\_primary.dat
.......\..........\........\........\.........\_primary.dbs
.......\..........\........\........\.........\_primary.vhd
.......\..........\........\........\.p_top\verilog.prw
.......\..........\........\........\......\verilog.psm
.......\..........\........\........\......\_primary.dat
.......\..........\........\........\......\_primary.dbs
.......\..........\........\........\......\_primary.vhd
.......\..........\........\........\......_vlg_tst\verilog.prw
.......\..........\........\........\..............\verilog.psm
.......\..........\........\........\..............\_primary.dat
.......\..........\........\........\..............\_primary.dbs
.......\..........\........\........\..............\_primary.vhd
.......\..........\........\........\_info
.......\..........\........\........\_vmake
.......\..........\........\sp_top.sft
.......\..........\........\sp_top.vo
.......\..........\........\sp_top.vt
.......\..........\........\sp_top.vt.bak
.......\..........\........\sp_top_modelsim.xrf
.......\..........\........\sp_top_run_msim_rtl_verilog.do
.......\..........\........\sp_top_run_msim_rtl_verilog.do.bak
.......\..........\.