文件名称:FSK
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推荐一个FSK解调工程，用Actel FPGA 实现的比较通用，VHDL 源代码。-Recommended Actel FPGA implementation FSK demodulator engineering, more generic, VHDL realization.
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下载文件列表
FSK
...\FSK.prj
...\component
...\constraint
...\coreconsole
...\designer
...\........\impl1
...\........\.....\FSK.ide_des
...\........\.....\PLL_device.ide_des
...\........\.....\PLL_device.tcl
...\........\.....\delay.ide_des
...\........\.....\designer_synth_check.log
...\........\.....\simulation
...\........\.....\testbench.ide_des
...\hdl
...\...\FSK.vhd
...\phy_synthesis
...\simulation
...\..........\modelsim.ini
...\..........\modelsim.ini.sav
...\..........\modelsim.log
...\..........\postsynth
...\..........\.........\_info
...\..........\.........\_temp
...\..........\.........\_vmake
...\..........\.........\pll_device
...\..........\.........\..........\_primary.dat
...\..........\.........\..........\_primary.dbs
...\..........\.........\..........\def_arch.dat
...\..........\.........\..........\def_arch.dbs
...\..........\.........\..........\def_arch.prw
...\..........\.........\..........\def_arch.psm
...\..........\.........\testbench
...\..........\.........\.........\_primary.dat
...\..........\.........\.........\_primary.dbs
...\..........\.........\.........\siml.dat
...\..........\.........\.........\siml.dbs
...\..........\.........\.........\siml.prw
...\..........\.........\.........\siml.psm
...\..........\presynth
...\..........\........\_info
...\..........\........\_temp
...\..........\........\_vmake
...\..........\........\pll_device
...\..........\........\..........\_primary.dat
...\..........\........\..........\_primary.dbs
...\..........\........\..........\def_arch.dat
...\..........\........\..........\def_arch.dbs
...\..........\........\..........\def_arch.prw
...\..........\........\..........\def_arch.psm
...\..........\........\testbench
...\..........\........\.........\_primary.dat
...\..........\........\.........\_primary.dbs
...\..........\........\.........\siml.dat
...\..........\........\.........\siml.dbs
...\..........\........\.........\siml.prw
...\..........\........\.........\siml.psm
...\..........\run.do
...\..........\vsim.wlf
...\smartgen
...\........\PLL_device
...\........\..........\PLL_device.cxf
...\........\..........\PLL_device.gen
...\........\..........\PLL_device.log
...\........\..........\PLL_device.vhd
...\........\PLL_device_work.ixf
...\........\delay
...\........\.....\delay.cxf
...\........\.....\delay.gen
...\........\.....\delay.log
...\........\.....\delay.vhd
...\........\delay_work.ixf
...\........\smartgen.aws
...\stimulus
...\........\testbench.vhd
...\synthesis
...\.........\.recordref
...\.........\PLL_device.areasrr
...\.........\PLL_device.edn
...\.........\PLL_device.fse
...\.........\PLL_device.htm
...\.........\PLL_device.map
...\.........\PLL_device.pdc
...\.........\PLL_device.sdf
...\.........\PLL_device.so
...\.........\PLL_device.srd
...\.........\PLL_device.srl
...\.........\PLL_device.srm
...\.........\PLL_device.srr
...\.........\PLL_device.srs
...\.........\PLL_device.szr
...\.........\PLL_device.tlg
...\.........\PLL_device.vhd
...\.........\PLL_device_sdc.sdc
...\.........\PLL_device_syn.prd
...\.........\PLL_device_syn.prj
...\.........\backup
...\.........\......\PLL_device.srr
...\.........\coreip
...\.........\dm