文件名称:ethernet
介绍说明－－下载内容均来自于网络，请自行研究使用
一个典型的以太网的VHDL程序，非常有参考价值！！
-A typical Ethernet VHDL program, a very valuable reference! !
-A typical Ethernet VHDL program, a very valuable reference! !
(系统自动生成,下载前可以参看下载内容)
下载文件列表
ethernet\ethernet\bench\CVS\Entries
........\........\.....\...\Repository
........\........\.....\...\Root
........\........\.....\CVS
........\........\.....\verilog\CVS\Entries
........\........\.....\.......\...\Repository
........\........\.....\.......\...\Root
........\........\.....\.......\CVS
........\........\.....\.......\eth_host.v
........\........\.....\.......\eth_memory.v
........\........\.....\.......\eth_phy.v
........\........\.....\.......\eth_phy_defines.v
........\........\.....\.......\tb_cop.v
........\........\.....\.......\tb_ethernet.v
........\........\.....\.......\tb_ethernet_with_cop.v
........\........\.....\.......\tb_eth_defines.v
........\........\.....\.......\tb_eth_top.v
........\........\.....\.......\wb_bus_mon.v
........\........\.....\.......\wb_master32.v
........\........\.....\.......\wb_master_behavioral.v
........\........\.....\.......\wb_model_defines.v
........\........\.....\.......\wb_slave_behavioral.v
........\........\.....\verilog
........\........\bench
........\........\CVS\Entries
........\........\...\Repository
........\........\...\Root
........\........\CVS
........\........\doc\CVS\Entries
........\........\...\...\Repository
........\........\...\...\Root
........\........\...\CVS
........\........\...\ethernet_datasheet_OC_head.pdf
........\........\...\ethernet_product_brief_OC_head.pdf
........\........\...\eth_design_document.pdf
........\........\...\eth_speci.pdf
........\........\...\src\CVS\Entries
........\........\...\...\...\Repository
........\........\...\...\...\Root
........\........\...\...\CVS
........\........\...\...\ethernet_datasheet_OC_head.doc
........\........\...\...\ethernet_product_brief_OC_head.doc
........\........\...\...\eth_design_document.doc
........\........\...\...\eth_speci.doc
........\........\...\src
........\........\doc
........\........\README.txt
........\........\rtl\CVS\Entries
........\........\...\...\Repository
........\........\...\...\Root
........\........\...\CVS
........\........\...\verilog\BUGS
........\........\...\.......\CVS\Entries
........\........\...\.......\...\Repository
........\........\...\.......\...\Root
........\........\...\.......\CVS
........\........\...\.......\eth_clockgen.v
........\........\...\.......\eth_cop.v
........\........\...\.......\eth_crc.v
........\........\...\.......\eth_defines.v
........\........\...\.......\eth_fifo.v
........\........\...\.......\eth_maccontrol.v
........\........\...\.......\eth_macstatus.v
........\........\...\.......\eth_miim.v
........\........\...\.......\eth_outputcontrol.v
........\........\...\.......\eth_random.v
........\........\...\.......\eth_receivecontrol.v
........\........\...\.......\eth_register.v
........\........\...\.......\eth_registers.v
........\........\...\.......\eth_rxaddrcheck.v
........\........\...\.......\eth_rxcounters.v
........\........\...\.......\eth_rxethmac.v
........\........\...\.......\eth_rxstatem.v
........\........\...\.......\eth_shiftreg.v
........\........\...\.......\eth_spram_256x32.v
........\........\...\.......\eth_top.v
........\........\...\.......\eth_transmitcontrol.v
........\........\...\.......\eth_txcounters.v
........\........\...\.......\eth_txethmac.v
........\........\...\.......\eth_txstatem.v
........\........\...\.......\eth_wishbone.v
........\........\...\.......\timescale.v
........\........\...\.......\TODO
........\........\...\.......\xilinx_dist_ram_16x32.v
........\........\...\verilog
........\........\rtl
........\........\sim\CVS\Entries
........\........\...\...\Repository
........\........\...\...\Root
........\........\...\CVS
........\........\...\rtl_sim\bin\artisan_file_list.lst
........\........\...\.......\...\cds.lib
........\........\...\.......\...\CVS\Entries
........\........\...\.......\...\...\Repository
........\........\...\.......\...\...\Root
........\........\...\.......\...\CVS
........\........\...\.......\...\hdl.var
........\........\...\.......\...\INCA_libs\CVS\Entries
........\........\...\.......\...\.........\...\Repository
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