文件名称:123
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基于FPGA的简单计算器系统的设计，使用了vhdl与verilog语言，附有文档介绍-Simple calculator system based on FPGA design using vhdl verilog language, with document describes
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..........\ALU.bsf
..........\ALU.vhd
..........\ALU.vhd.bak
..........\circlekeyboard.bsf
..........\circlekeyboard.v
..........\clr_control.bsf
..........\ctrlunit.bsf
..........\ctrlunit.cvwf
..........\ctrlunit.vhd
..........\ctrlunit.vhd.bak
..........\ctrlunit.vwf
..........\d258496ecc7d8ebc77c34c44d7a22cb5.png
..........\data.bsf
..........\data.vhd
..........\data.vhd.bak
..........\db
..........\..\abs_divider_mbg.tdf
..........\..\add_sub_lkc.tdf
..........\..\add_sub_mkc.tdf
..........\..\altsyncram_1uo1.tdf
..........\..\altsyncram_gra1.tdf
..........\..\altsyncram_koa1.tdf
..........\..\altsyncram_r4a1.tdf
..........\..\altsyncram_sr61.tdf
..........\..\altsyncram_t0p1.tdf
..........\..\alt_u_div_k5f.tdf
..........\..\alt_u_div_o2f.tdf
..........\..\clr_control.vhd
..........\..\clr_control.vhd.bak
..........\..\decode_n6f.tdf
..........\..\decode_s6f.tdf
..........\..\lpm_abs_2s9.tdf
..........\..\lpm_abs_gq9.tdf
..........\..\lpm_divide_28m.tdf
..........\..\lpm_divide_9so.tdf
..........\..\lpm_ram_256_8.bdf
..........\..\mux_3nc.tdf
..........\..\mux_4nc.tdf
..........\..\mux_joc.tdf
..........\..\mux_mmc.tdf
..........\..\mux_smc.tdf
..........\..\mux_vmc.tdf
..........\..\prev_cmp_projece_a.archive.qmsg
..........\..\prev_cmp_projece_a.asm.qmsg
..........\..\prev_cmp_projece_a.fit.qmsg
..........\..\prev_cmp_projece_a.map.qmsg
..........\..\prev_cmp_projece_a.qmsg
..........\..\prev_cmp_projece_a.sim.qmsg
..........\..\prev_cmp_projece_a.tan.qmsg
..........\..\projece_a.archive.qmsg
..........\..\projece_a.asm.qmsg
..........\..\projece_a.asm_labs.ddb
..........\..\projece_a.cbx.xml
..........\..\projece_a.cmp.bpm
..........\..\projece_a.cmp.cdb
..........\..\projece_a.cmp.ecobp
..........\..\projece_a.cmp.hdb
..........\..\projece_a.cmp.kpt
..........\..\projece_a.cmp.logdb
..........\..\projece_a.cmp.rdb
..........\..\projece_a.cmp.tdb
..........\..\projece_a.cmp0.ddb
..........\..\projece_a.cmp2.ddb
..........\..\projece_a.cmp_merge.kpt
..........\..\projece_a.db_info
..........\..\projece_a.eco.cdb
..........\..\projece_a.eds_overflow
..........\..\projece_a.fit.qmsg
..........\..\projece_a.fnsim.hdb
..........\..\projece_a.fnsim.qmsg
..........\..\projece_a.hier_info
..........\..\projece_a.hif
..........\..\projece_a.lpc.html
..........\..\projece_a.lpc.rdb
..........\..\projece_a.lpc.txt
..........\..\projece_a.map.bpm
..........\..\projece_a.map.cdb
..........\..\projece_a.map.ecobp
..........\..\projece_a.map.hdb
..........\..\projece_a.map.kpt
..........\..\projece_a.map.logdb
..........\..\projece_a.map.qmsg
..........\..\projece_a.map_bb.cdb
..........\..\projece_a.map_bb.hdb
..........\..\projece_a.map_bb.logdb
..........\..\projece_a.pre_map.cdb
..........\..\projece_a.pre_map.hdb
..........\..\projece_a.rtlv.hdb
..........\..\projece_a.rtlv_sg.cdb
..........\..\projece_a.rtlv_sg_swap.cdb
..........\..\projece_a.sgdiff.cdb
..........\..\projece_a.sgdiff.hdb
..........\..\projece_a.sim.cvwf
..........\..\projece_a.sim.hdb
..........\..\projece_a.sim.qmsg
..........\..\projece_a.sim.rdb
..........\..\projece_a.simfam
..........\..\projece_a.sld_design_entry.sci
..........\..\projece_a.sld_design_entry_dsc.sci