文件名称:simple_clock
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基于ｆｐｇａ的简单时钟，可以作为本科课程设计的内容，用ｖｅｒｉｌｏｇ编写的-Fpga-based simple clock, as the content of the undergraduate curriculum design with verilog prepared
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下载文件列表
simple_clock
............\simple_clock
............\............\db
............\............\..\main_test.ae.hdb
............\............\..\main_test.cbx.xml
............\............\..\main_test.cmp.rdb
............\............\..\main_test.db_info
............\............\..\main_test.eco.cdb
............\............\..\main_test.hier_info
............\............\..\main_test.hif
............\............\..\main_test.lpc.html
............\............\..\main_test.lpc.rdb
............\............\..\main_test.lpc.txt
............\............\..\main_test.map.qmsg
............\............\..\main_test.pre_map.cdb
............\............\..\main_test.pre_map.hdb
............\............\..\main_test.rtlv.hdb
............\............\..\main_test.rtlv_sg.cdb
............\............\..\main_test.rtlv_sg_swap.cdb
............\............\..\main_test.sld_design_entry.sci
............\............\..\main_test.sld_design_entry_dsc.sci
............\............\..\main_test.sta.qmsg
............\............\..\main_test.tan.qmsg
............\............\..\main_test.tmw_info
............\............\..\prev_cmp_main_test.map.qmsg
............\............\..\prev_cmp_main_test.qmsg
............\............\incremental_db
............\............\..............\compiled_partitions
............\............\..............\README
............\............\main_test.done
............\............\main_test.flow.rpt
............\............\main_test.map.rpt
............\............\main_test.map.summary
............\............\main_test.qpf
............\............\main_test.qsf
............\............\main_test.qws
............\............\src
............\............\...\control.vhd
............\............\...\controlen.vhd
............\............\...\counter.vhd
............\............\...\count_10.vhd
............\............\...\count_10_6_10_10.vhd
............\............\...\count_6.vhd
............\............\...\decoder.vhd
............\............\...\display.vhd
............\............\...\fen_pin.vhd
............\............\...\main_control.vhd
............\............\...\main_test.vhd
............\simple_clock_modelsim
............\.....................\rsc
............\.....................\...\clock_counter.v
............\.....................\...\clock_set.v
............\.....................\...\clock_top.v
............\.....................\...\counter_6.v
............\.....................\...\decoder3_8.v
............\.....................\...\hour_decoder.v
............\.....................\...\led_display.v
............\.....................\...\led_display.v.bak
............\.....................\...\mux6_1.v
............\.....................\...\mux6_1.v.bak
............\.....................\...\nomal_decoder.v
............\.....................\simple_clock_modelsim.cr.mti
............\.....................\simple_clock_modelsim.mpf
............\.....................\work
............\.....................\....\clock_counter
............\.....................\....\.............\_primary.dat
............\.....................\....\.............\_primary.dbs
............\.....................\....\.............\_primary.vhd
............\.....................\....\clock_set
............\.....................\....\.........\_primary.dat
............\.....................\....\.........\_primary.dbs
............\.....................\....\.........\_primary.vhd
............\.....................\....\clock_top
............\.....................\....\.........\_primary.dat
............\.....................\....\.........\_primary.dbs
............\.....................\....\.........\_primary.vhd
............\.....................\....\counter_6
............\.....................\....\.........\_primary.dat
............\.....................\....\.........\_primary.dbs
............\.....................\....\.........\_primary.vhd
............\.....................\....\decoder3_8
............\.....................\....\..........\_primary.dat
.........