文件名称:Hhdlc_latesttD
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HDLC在通讯设备中占有重要地位，本文件提供了完整正正确的HDLC的硬件逻辑设计！对设计和学习都具有参考价值
-HDLC occupies an important position in the communications equipment provided in this document is correct complete HDLC hardware logic design! Reference value of design and learning
-HDLC occupies an important position in the communications equipment provided in this document is correct complete HDLC hardware logic design! Reference value of design and learning
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下载文件列表
Hhdlc_latesttD\trunk\CODE\LIBS\hdlc_components_pkg.vhd
..............\.....\....\....\PCK_CRC16_D8.vhd
..............\.....\....\MEM_PKG.VHD
..............\.....\....\RX\CORE\flag_detect.vhd
..............\.....\....\..\....\RxChannel.vhd
..............\.....\....\..\....\Rxcont.vhd
..............\.....\....\..\....\Zero_detect.vhd
..............\.....\....\..\SCRIPTS\WAVE.DO
..............\.....\....\..\TB\Rx_tb.vhd
..............\.....\....\SPMEM.VHD
..............\.....\....\tools_pkg.vhd
..............\.....\....\TOP\core\hdlc.vhd
..............\.....\....\...\....\RxBuff.vhd
..............\.....\....\...\....\RxFCS.vhd
..............\.....\....\...\....\RxSync.vhd
..............\.....\....\...\....\TxBuff.vhd
..............\.....\....\...\....\TxFCS.vhd
..............\.....\....\...\....\TxSync.vhd
..............\.....\....\...\....\WB_IF.vhd
..............\.....\....\...\scripts\model\build_hdlc_top.do
..............\.....\....\...\.......\.....\build_TxFCS_Buff.do
..............\.....\....\...\.......\.....\wave.do
..............\.....\....\...\.......\nc-sim\build_hdlc_top.csh
..............\.....\....\...\.......\......\build_RxFCS_Buff.csh
..............\.....\....\...\.......\......\build_TxFCS_Buff.csh
..............\.....\....\...\.......\......\cds.lib
..............\.....\....\...\.......\......\hdl.var
..............\.....\....\...\tb\hdlc_tb.vhd
..............\.....\....\...\..\RxTop_tb.vhd
..............\.....\....\...\..\TxTop_tb.vhd
..............\.....\....\.X\core\flag_ins.vhd
..............\.....\....\..\....\TxChannel.vhd
..............\.....\....\..\....\TXcont.vhd
..............\.....\....\..\....\zero_ins.vhd
..............\.....\....\..\scripts\wave.do
..............\.....\....\..\tb\tx_tb.vhd
..............\.....\DOCS\hdlc_features.txt
..............\.....\....\hdlc_project.pdf
..............\.....\....\hdlc_project.tex
..............\.....\....\HDLC_top.dia
..............\.....\ETC\HDLC_top.jpg
..............\.....\CODE\TOP\scripts\model
..............\.....\....\...\.......\nc-sim
..............\.....\....\RX\CORE
..............\.....\....\..\SCRIPTS
..............\.....\....\..\TB
..............\.....\....\TOP\core
..............\.....\....\...\scripts
..............\.....\....\...\tb
..............\.....\....\.X\core
..............\.....\....\..\scripts
..............\.....\....\..\tb
..............\.....\....\LIBS
..............\.....\....\RX
..............\.....\....\TOP
..............\.....\....\TX
..............\.....\CODE
..............\.....\DOCS
..............\.....\ETC
..............\trunk
Hhdlc_latesttD