文件名称:8b10encode

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [PDF]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 763kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 阿**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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8b10b编码器是设计高速数据发送的重要编码方式,其中有源代码还有具体设计文档-8b10b encoder design of high-speed data transmission encoding, including source code, there are specific design documents
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下载文件列表





RD1012_rev01.2\docs

..............\....\rd1012.pdf

..............\....\rd1012_readme.txt

..............\project

..............\.......\4k

..............\.......\..\verilog

..............\.......\..\.......\8b_10b_enc_dec.lct

..............\.......\..\vhdl

..............\.......\..\....\8b_10b_enc_dec.lct

..............\.......\ecp_ec

..............\.......\......\verilog

..............\.......\......\.......\8b_10b_enc_dec.lpf

..............\.......\......\vhdl

..............\.......\......\....\8b_10b_enc_dec.lpf

..............\.......\ecp2m

..............\.......\.....\verilog

..............\.......\.....\.......\enc_dec.lpf

..............\.......\.....\.......\Strategy1.sty

..............\.......\.....\vhdl

..............\.......\.....\....\enc_dec.lpf

..............\.......\.....\....\Strategy1.sty

..............\.......\ecp3

..............\.......\....\verilog

..............\.......\....\.......\enc_dec.lpf

..............\.......\....\.......\Strategy1.sty

..............\.......\....\vhdl

..............\.......\....\....\enc_dec.lpf

..............\.......\....\....\Strategy1.sty

..............\.......\xo

..............\.......\..\verilog

..............\.......\..\.......\8b_10b_enc_dec.lpf

..............\.......\..\vhdl

..............\.......\..\....\8b_10b_enc_dec.lpf

..............\.......\xo2

..............\.......\...\verilog

..............\.......\...\.......\enc_dec.lpf

..............\.......\...\.......\Strategy1.sty

..............\.......\...\vhdl

..............\.......\...\....\enc_dec.lpf

..............\.......\...\....\Strategy1.sty

..............\.......\xp2

..............\.......\...\verilog

..............\.......\...\.......\enc_dec.lpf

..............\.......\...\.......\Strategy1.sty

..............\.......\...\vhdl

..............\.......\...\....\enc_dec.lpf

..............\.......\...\....\Strategy1.sty

..............\simulation

..............\..........\4k

..............\..........\..\verilog

..............\..........\..\.......\tb_top_net_8b10b_tfa.udo

..............\..........\..\.......\tb_top_net_8b10b_tffa.udo

..............\..........\..\vhdl

..............\..........\..\....\tb_top_net_8b10b_vhda.udo

..............\..........\..\....\tb_top_net_8b10b_vhdaf.udo

..............\..........\ecp_ec

..............\..........\......\verilog

..............\..........\......\.......\tb_top_net_8b10b_tf.udo

..............\..........\......\.......\tb_top_net_8b10b_tff.udo

..............\..........\......\vhdl

..............\..........\......\....\tb_top_net_8b10b_vhd.udo

..............\..........\......\....\tb_top_net_8b10b_vhdf.udo

..............\..........\ecp2m

..............\..........\.....\verilog

..............\..........\.....\.......\enc_dec_enc_dec_vo.sdf

..............\..........\.....\.......\enc_dec_enc_dec_vo.vo

..............\..........\.....\.......\rtlsim.do

..............\..........\.....\.......\timesim.do

..............\..........\.....\vhdl

..............\..........\.....\....\enc_dec_enc_dec_vho.sdf

..............\..........\.....\....\enc_dec_enc_dec_vho.vho

..............\..........\.....\....\rtlsim.do

..............\..........\.....\....\timesim.do

..............\..........\ecp3

..............\..........\....\verilog

..............\..........\....\.......\enc_dec_enc_dec_vo.sdf

..............\..........\....\.......\enc_dec_enc_dec_vo.vo

..............\..........\....\.......\rtlsim.do

..............\..........\....\.......\timesim.do

..............\..........\....\vhdl

..............\..........\....\....\enc_dec_enc_dec_vho.sdf

..............\..........\....\....\enc_dec_enc_dec_vho.vho

..............\..........\....\....\rtlsim.do

..............\..........\....\....\timesim.do

..............\..........\xo

..............\..........\..\verilog

..............\..........\..\.......\tb_top_net_8b10b_tf.udo

..............\..........\..\.......\tb_top_net_8b10b_tff.udo

..............\..........\..\vhdl

..............\..........\..\....\tb_top_net_8b10b_vhd.udo

..............\..........\..\....\tb_top_net_8b10b_vhdf.udo

..............\..........\xo2

..............\..........\...\

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